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7

A PLL on its own will not work on the direct PSK modulation, assuming the symbols are equi-probable as that results in a nulled carrier, so there is nothing the PLL can track! Costas-Loops are effective for BPSK and QPSK implementations, and as Dilip had suggested, for BPSK you can square your signal and then use a PLL to lock onto the 2F frequency that ...


5

To track a frequency ramp with a Phase lock loop, with zero steady state error requires a type 3 PLL Loop; which means three integrations (DC Poles) in the open loop gain (your NCO would be one of the integrators and your loop filter needs to provide the other two). Stabilizing such a system becomes more challenging but here is one reference paper detailing ...


5

For very high SNR signals locating the zero crossings will work pretty well. You use PLL's when the signal doesn't have a high SNR, like the following. As you can see by inspection, a zero-crossing algorithm wouldn't have a prayer of working on this signal. A PLL, on the other hand, could do just fine. That is, by the way, a tone with an SNR of 8 dB.


5

You are having trouble because that's not a Costas loop. A Costas loop uses demodulated data in some form to change the phase that's expected from the signal. You're just taking the I/Q demodulated signal and applying it to the atan2 function; that makes a sort of linearized extended phase detector, but without determining that the phase should have ...


5

A step response test is an easy way to determine the bandwidth. Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected response at the output of the loop filter as shown in this block diagram. Note that the loop will respond in such a way to completely cancel the injected offset, but ...


4

Notice that CORDIC operates digitally, it is more about a type of processor with a very simple instruction set that allows you to compute different functions. The CORDIC was a great idea to make it possible to implement different arithmetic functions in early calculators. It is advantageous when you need to implement it with the least number of transistors. ...


4

Below is an intuitive explanation to the CORDIC. The CORDIC algorithm, published by Jack Volder in 1959 (Coordinate Rotation Digital Computer), allows rotating a phasor with only shifts and adds and can be used for phasor rotation, trigonometric calculation and computing the magnitude of of a complex phasor without the use of multipliers. To see the ...


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The question is specific to optimizing loop bandwidth for the decision directed carrier tracking loop with one sample per symbol. In other posts such as this one PLL for Phase Demodulation and Carrier Tracking I have detailed the consideration for not making the loop bandwidth too low due to increasing contributions from LO phase noise as well as less ...


3

I want to know how in practice we can take a kHz/MHz signal to a GHz band? You guessed right: a mixer. Should I build an oscillator with a frequency of 3499700 kHz (or 3480 MHz) to use it as a mixer? Assuming these frequencies are the difference between your source and your target frequencies, yes. But you don't use an oscillator as a mixer, you use ...


3

Before I address your questions, you should understand: a. the integral branch of the loop filter maintains a average phase increment in units of radians/sample. It is not a frequency value, though in the right context it can be converted to a frequency value, using your sample rate as a conversion factor. b. the total output of the loop filter is an ...


3

I faced the same problem in the past. Perhaps there is a way without adding a delay but I haven't found it. You need to realize that your 3 first solutions (delay after vq, delay at the delta_freq and delay after the frequency) will yield the same result as omega_g is a constant and because your PI controller has fixed coefficients. Anyway, place the ...


3

There are three different kinds of synchronization in a passband digital communications system: Carrier synchronization: the receiver needs to know the exact frequency and phase of the carrier used by the transmitter. Symbol synchronization: the receiver needs to know the optimum instants to sample the matched filter's output. Frame synchronization: the ...


3

Assuming we have timing recovery resolved (meaning our system knows the correct time locations for our symbol decisions), then we can use the decided symbols along with our pre-decision values in a Decision-Directed Phase Detector. This will give us an error value that we can then feed into a phase lock loop to correct for phase error using traditional PLL ...


3

Two suggestions to move forward: Reduce $K_i$ to the point of an acceptable overshoot (this will provide the bottom line answer for comparison to the computations. Do system identification (Bode plots) on the open loop system and individual components to isolate the difference between implementation and loop model; the computations were compared below ...


2

You should just use a notch filter. Below shows two sinusoids added together (top) and the result of filtering the lower frequency one (bottom). The filter is just: $$ H(z) = \frac{1 - 2 \cos(2\pi \omega_{b}) z^{-1} + z^{-2}} {1 - 2 \alpha \cos(2\pi \omega_{b}) z^{-1} + \alpha^2z^{-2}} $$ where $\omega_b$ is the bad frequency and $\alpha<1.0$ is related ...


2

I can only answer your second question: "How can the loop bandwidth in GNU Radio synchronization be configured as a percentage of the symbol rate?" The tracking loop in the symbol synchronizer block operates at the symbol rate, estimating timing error and making a correction once per symbol. So the sample rate of the error signal from the TED is at ...


2

Typically, phase ambiguity arises in the demodulation process when the carrier recovery is done via a loop that tracks the fourth harmonic of the received signal. So why can't the loop track the carrier frequency directly? Well, the received signal doesn't have a carrier signal -- it has a modulated carrier signal whose phase is going to change at every ...


2

Yes this is very common to have a dynamic loop bandwidth such that during acquisition the loop bandwidth is wider, and then once acquired to tighten it up for better noise performance. A typical loop will have an error signal determined which is presented to the input of the loop filter. The filtered version of this error signal can be thresholded and used ...


2

It seems like your error jumps to -$\pi$ and then to $\pi$ I think you need to unwrap your phase. Let me explain with an example Say that the output of atan2 block is $\pi - 0.001$ and then the phase difference increases by 0.002 rad, the outuput of the atan 2 block should then be $\pi$ + 0.001, however the atan2 output is limited to ±$\pi$. Therefore the ...


2

I will assume that your PLL is purely digital. Is that correct? I assume your PLL consists of 3 blocks The first block calculates the phase of your incoming signal (the signal you wanna lock to). The second one will compare the phase of the signal to the phase of your "internal oscillator" yielding the error e[n] The third one is your "controller" which ...


2

One approach is to use a phase/frequency detector as the circuit determining error and to ensure that the initial loop bandwidth is wide enough to “see” both the weaker signal that would otherwise be a false acquisition as well as the strongest signal desired. The loop will lock onto the strongest signal within the loop bandwidth as long as it is 6 dB above ...


2

The multibit reference signal is typically not sinusoidal, can have offset and substantial noise, but is expected to contain one dominant frequency. Against offset, you'd practically always start your processing with a high-pass filter. If you know your dominant frequency to be sufficiently less than Nyquist, a fixed low-pass filter would also be a cheap ...


2

This is just a different flavor of what Dan Boschen suggests. In fact, the actual summing junction part is exactly what he's suggesting. Insert a summing junction, and then inject a signal ($u_A$ in my diagram). For more work, you can get the frequency response directly. If you inject a sine wave at $u_A$ while you pick off $u_R$ and $y$, you can let it ...


2

Costas loop (and other PLL-based synchronization algorithms) tend to lose lock when the frequency offset is higher than the pull-in range (i.e. maximum frequency offset the said algorithm can cope with). Thus, a coarse frequency recovery algorithm is typically included in practice. The general practice is to put the coarse frequency recovery before the ...


2

I recommend a standard dq-PLL, check this reference https://vbn.aau.dk/ws/portalfiles/portal/273236528/PLL_Review_RSER.pdf There are 2 required integrators. For algebraic loop reasons, the last integrator, the one that converts the angular frequency to the phase, should be a forward-Euler integrator. The integrator in the PI controller, can be a trapezoidal ...


2

1 There's a mistake in the PID connection. You must feed the quadrature component, i.e $U_q$ to the PID, not $U_d$. The setpoint of your PLL is $U_q = 0$ because you want your PLL to be in phase with your 3-phase input i.e. $U_d = 1, U_q = 0$. 2 - Perhaps there are hidden delays in the block you instantiated ? 3 - Notice the error equation of your PLL is ...


2

Are the PI and IIR LPF filters equivalent? A PI filter is an IIR LPF, but a low-pass filter is more general. So -- no. Is my understanding of this "modified" PLL structure correct? I can't tell, but I think you're lacking in the understanding of closed-loop control systems. Should the IIR filter work in this case? Maybe, but it depends on ...


1

You seem to have 3 problems 1 - You have a phase wrap. It happens when the phase goes past 180 degrees. The phase will wrap back to -180 degrees. You can fix this by unwrapping the phase. 2 - Your phase is in normalized radians instead of being in radians or degrees. This is not a problem per se but when you try to unwrap the phase, you should be aware that ...


1

It is easy to overlook which sample is 'traveling' through the PLL in a for loop at a particular time. Have a look at the PLL block diagram and you will notice that the NCO output is the phase estimate delayed by one sample. Remember that the integrator in the PLL and the integrator in the NCO approximate the integration operation through different rules. ...


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