9
votes
High modulation index PSK - carrier recovery
A PLL on its own will not work on the direct PSK modulation, assuming the symbols are equi-probable as that results in a nulled carrier, so there is nothing the PLL can track! Costas-Loops are ...
- 55k
9
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How can I determine the frequency of a sine wave signal with gradually increasing frequency?
Instantaneous frequency is the time derivative of phase. Since the OP already has the analytic signal representation of the chirp, every sample can easily be used for the frequency estimate (unlike ...
- 55k
5
votes
How can I experimentally find the bandwidth of my PLL?
A step response test is an easy way to determine the bandwidth. Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected ...
- 55k
5
votes
CORDIC, What is it?
Below is an intuitive explanation to the CORDIC.
The CORDIC algorithm, published by Jack Volder in 1959 (Coordinate Rotation Digital Computer), allows rotating a phasor with only shifts and adds and ...
- 55k
5
votes
CORDIC, What is it?
Notice that CORDIC operates digitally, it is more about a type of processor with a very simple instruction set that allows you to compute different functions.
The CORDIC was a great idea to make it ...
- 2,393
5
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Transfer function of a PLL Loop Filter that can support a linearly increasing (chirping) frequency
To track a frequency ramp with a Phase lock loop, with zero steady state error requires a type 3 PLL Loop; which means three integrations (DC Poles) in the open loop gain (your NCO would be one of the ...
- 55k
5
votes
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Digital PLL loses lock every time mesage crosses zero
You are having trouble because that's not a Costas loop. A Costas loop uses demodulated data in some form to change the phase that's expected from the signal.
You're just taking the I/Q ...
- 13.3k
5
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How to set parameters of the PI controller inside the PLL?
Two suggestions to move forward:
Reduce $K_i$ to the point of an acceptable overshoot (this will provide the bottom line answer for comparison to the computations.
Do system identification (Bode ...
- 55k
5
votes
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Computing phase difference between two sinusoidal signals
The phase between the sine waves can be computed as suggested, at any sampling rate as long as it is greater than twice the sum of the frequency of the sine waves. Further the result is sensitive to ...
- 55k
4
votes
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Carrier Tracking Loop: Tracking noise vs Phase Noise Trade-off
The question is specific to optimizing loop bandwidth for the decision directed carrier tracking loop with one sample per symbol. In other posts such as this one PLL for Phase Demodulation and Carrier ...
- 55k
3
votes
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3
votes
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Is Phase Locked Loop is essential for BPSK signal reception?
There are three different kinds of synchronization in a passband digital communications system:
Carrier synchronization: the receiver needs to know the exact frequency and phase of the carrier used ...
- 15.4k
3
votes
SRF-PLL discretization problem
I faced the same problem in the past. Perhaps there is a way without adding a delay but I haven't found it.
You need to realize that your 3 first solutions (delay after vq, delay at the delta_freq ...
- 3,797
3
votes
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upconverting a kHz/MHz signal to GHz
I want to know how in practice we can take a kHz/MHz signal to a GHz band?
You guessed right: a mixer.
Should I build an oscillator with a frequency of 3499700 kHz (or 3480 MHz) to use it as a ...
- 32.5k
3
votes
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PLL phase and frequency characteristics
Before I address your questions, you should understand:
a. the integral branch of the loop filter maintains a average phase increment in units of radians/sample. It is not a frequency value, though ...
- 2,710
3
votes
How to set parameters of the PI controller inside the PLL?
1 There's a mistake in the PID connection. You must feed the quadrature component, i.e $U_q$ to the PID, not $U_d$. The setpoint of your PLL is $U_q = 0$ because you want your PLL to be in phase with ...
- 3,797
3
votes
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How are Loop Filters derived?
This is a very broad question where a book would be required to give a full answer. Let me try to give a very high level introduction into what a "Loop Filter" is and how it works using an ...
- 55k
3
votes
Accepted
A question regarding using analog PLL circuit with QAM modulation for phase sync
M-ary QAM assuming equiprobable data symbols has the carrier suppressed in both the in-phase and quadrature signals as well as the composite complex signal. Therefore a traditional PLL does not have ...
- 55k
2
votes
Phase ambiguity in QAM modulation
Typically, phase ambiguity arises in the demodulation process when the carrier recovery is done via a loop that tracks the fourth harmonic of the received signal. So why can't the loop track the ...
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2
votes
Digital PLL loses lock every time mesage crosses zero
It seems like your error jumps to -$\pi$ and then to $\pi$
I think you need to unwrap your phase. Let me explain with an example
Say that the output of atan2 block is $\pi - 0.001$ and then the ...
- 3,797
2
votes
NCO loses lock after a while for certain values of alpha
I will assume that your PLL is purely digital. Is that correct?
I assume your PLL consists of 3 blocks
The first block calculates the phase of your incoming signal (the signal you wanna lock to).
...
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2
votes
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GNU Radio loop bandwidth normalization
I can only answer your second question:
"How can the loop bandwidth in GNU Radio synchronization be configured as a percentage of the symbol rate?"
The tracking loop in the symbol synchronizer block ...
- 2,710
2
votes
Accepted
PLL for Phase Demodulation and Carrier Tracking
Yes this is very common to have a dynamic loop bandwidth such that during acquisition the loop bandwidth is wider, and then once acquired to tighten it up for better noise performance.
A typical ...
- 55k
2
votes
PLL: cycle slipping correction
Costas loop (and other PLL-based synchronization algorithms) tend to lose lock when the frequency offset is higher than the pull-in range (i.e. maximum frequency offset the said algorithm can cope ...
2
votes
How can I experimentally find the bandwidth of my PLL?
This is just a different flavor of what Dan Boschen suggests. In fact, the actual summing junction part is exactly what he's suggesting.
Insert a summing junction, and then inject a signal ($u_A$ in ...
- 13.3k
2
votes
Most efficient way to find single dominant frequency (without amplitude) in analog signal
The multibit reference signal is typically not sinusoidal, can have offset and substantial noise, but is expected to contain one dominant frequency.
Against offset, you'd practically always start ...
- 32.5k
2
votes
Most efficient way to find single dominant frequency (without amplitude) in analog signal
One approach is to use a phase/frequency detector as the circuit determining error and to ensure that the initial loop bandwidth is wide enough to “see” both the weaker signal that would otherwise be ...
- 55k
2
votes
Accepted
Phase locked loop for three phase grid
I recommend a standard dq-PLL, check this reference https://vbn.aau.dk/ws/portalfiles/portal/273236528/PLL_Review_RSER.pdf
There are 2 required integrators. For algebraic loop reasons, the last ...
- 3,797
2
votes
BPSK based audio digital communication system
I mean it's just acoustic waves through air
No it's not. Not unless you are operating in an anechoic chamber (which is unlikely). The total transfer function of your channel can be quite complicated. ...
- 48.2k
2
votes
using DPLL to track audio tones: configuration parameters?
Some random pointers
The signum function probably don't help here. PLLs can lock to any harmonic (not just the fundamental) and the signum function will generate lots and lots of harmonics and also ...
- 48.2k
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