# PLL: cycle slipping correction

i am working on a receiver in the space communication. Under low SNR, big frequency offset, phase offset. I started with phase/frequency correction. I used digital PLL and it doesn't work for it. I have read in the book by Rice about "cycle slip" and I can use slip detector in such case. But I dont understand how such detector can be implemented. Can someone provide some information /explanation about it?

Does anyone know the simplest algorithm for cycle slipping correction?

I have found in the book by Rice ( Appendix C) about the cycle slip -effect. I have never heard about it, but it describes perfectly what I get in my simulation of phase correction. Rice didn't provide information about how to correct this effect but mentioned it.

• There are many different loop designs that count as "digital PLL", and many different things that can be "slip detectors". Please edit your question to share what you actually tried or are planning on trying -- preferably in the form of a short mathematical description, block diagram, or image of a book page, rather than reams of code. Apr 9, 2021 at 14:45
• Could you provide more information like modulation scheme, Data rate, Doppler shift (and rate)? What recovery algorithm have you tried so far? Apr 9, 2021 at 23:52
• @MosesBrowneMwakyanjala I added Apr 10, 2021 at 19:27
• @TimWescott i added Apr 10, 2021 at 19:27

Costas loop (and other PLL-based synchronization algorithms) tend to lose lock when the frequency offset is higher than the pull-in range (i.e. maximum frequency offset the said algorithm can cope with). Thus, a coarse frequency recovery algorithm is typically included in practice. The general practice is to put the coarse frequency recovery before the Costas loop. There are many ways of doing coarse frequency recovery including FFT-based algorithms and the frequency-locked loop (FLL) (described in Harris paper. My favorite is FFT due to its generality. The FFT algorithm can be found on the GOES satellite user manual and is summarized in the figure below. The algorithm works by:

1. Carrier detection by absolute-law (residual carrier), square-law (BPSK) or fourth-power law (QPSK). Square law detector involves squaring the IQ signal while fourth-power law uses the fourth-power of the IQ signal.
2. Finding the FFT
3. Averaging successive FFT sequences
4. Finding the peak by looking at 8 adjacent bins with the highest magnitude.

Below is a GNU Radio example for BPSK (square law). As you can see, an FFT is included at the very beginning to reduce the frequency offset (in my case it was Doppler shift/rate + carrier oscillator offset).

If you are interested, you could have a look at a paper I wrote a couple of years ago. The paper covers all aspects of synchronization including phase, frequency, and timing.

I hope this helps. Good luck.