I'm digitizing a zero-mean complex Gaussian white noise signal with certain variance, through independent I/Q baseband sampling (two ADCs).
The noise variance (power) depends on the thermal emission/signal of a certain microwave body, so out of the ADC I want to be able to compute the signal power to gain information of the sensed body.
I will average ADC output samples during a certain time to reduce noise; this integration time being certainly much larger than the ADC sampling period, so I expect to gain something there.
How to design the number of bits of the ADC?
I know that the input will be Gaussian (or let's assume so, in fact it will be band-limited) and that increasing the integration time or number of averaged samples will help in decreasing the variance in the estimation of the power.
Integrating for an infinite number of samples will make my estimation effectively constant (I guess I'm getting rid of quantization noise).
However, the number of bits will have a direct impact on the bias of this power estimation. Depending on the input signal power and the number of bits the output retrieved signal power will have different values.
There is probably little that I can do with averaging (I will not adjust the gain before the ADC), so that signals that occupy less of the ADC full scale will inevitably suffer from stronger biases. Am I missing something?