I'm doing the gain budget for a receiver that feeds into an ADC. I want to know what the best input range should be into the ADC so that I can detect down to the MDS (minimum discernible signal) while minimizing ADC spurious output content in my detection bandwidth.

Suppose for discussion sake that the ADC has a 1 volt full scale, 10 bits real and 8 bits ENOB.

Downstream processing uses very narrow band filtering (assume 128 evenly spaced channels), so I will get an improvement in the noise floor from that within the detection bandwidth. I'll assume thermal and quantization noise has a uniform spectral density.

I'd like my MDS to be determined by the uniform noise content and not by any additional ADC spurious content. This is a multi-channel receiver, so I would expect ADC spurious content to potentially fall within some channels.

My question is

  • Should I operate the ADC as an 8 bit ADC with full scale of 0.25 volts and set my noise into the ADC close to the quantization level and only use the lowest 8 bits, or
  • Should I operate with noise closer to 4 times the q level and use the highest 8 bits?
  • Or is there something else I need to be concerned about?

Basically what I'm trying to determine is will the ADC spurious out be any lower in one case vs the other, within my detection bandwidth?


1 Answer 1


Bottom Line

The OP wishes to determine the optimum level at which to set the waveform (typically the set point for Automatic Gain Control, or AGC) which can be referenced to "Full Scale" for the Analog to Digital Converter (ADC). Full Scale can be the power level at which a sinusoidal input would start to clip (referenced below as "Full Scale Sine Wave"), or the power level where a DC level would clip ("Full Scale DC"). The optimum level is a matter of minimizing the sum of noise due to clipping with noise due to quantization. Clipping noise is very dependent on the actual distribution of the waveform; many modern waveforms (such as OFDM for example) are Gaussian distributed, and for that condition as detailed below with an 8 bit effective number of bits (ENOB) the AGC set point would be 9 dB below a full scale sine wave.

So if the ADC was indeed 1V at full scale (which is +10 dBm assuming a 50 ohm input), then the optimized input level would be at +1 dBm. The ADC is 10 bits with 8 bits ENOB, and all 10 bits would be used in the subsequent processing. If there were some efficiency constraints where it is desired to use only 8 bits, it would be the lowest 2 bits that could be dropped.

The consideration of actual spurious content (noise power from the non-ideal actual sampler that is isolated to single frequency tones) does not change the ideal set point above, but changes how much the noise can be reduced after sampling due to filtering. The OP's assumption that a given spur can fall into any arbitrary band is a reasonable approach, and the Spurious Free Dynamic Range of the ADC (a parameter given on the datasheet) is indicative of what minimum discernable signal can be obtained for the case of narrow band signals where ultimately a spur will compete with the detection of a desired signal.

Further Details

The ENOB is 8 bits, but you would use all 10 bits available. It is just the total noise in that 10 bits is equivalent to what you would get with a "perfect" 8 bit converter, but this does not mean you should just drop the two LSBs. However for determining set-point (rms level of the waveform being sampled relative to full scale of the ADC) we would assume a perfect 8 bit converter. The set point will be in dB below full scale as an analog level at the input to the ADC, so it really won't matter in terms of determining and setting that how many bits are actually used.

Please see this existing post which has further details on this optimization curve for AGC set-point (where to set the rms level of the waveform) relative to full scale for the A/D Converter:

AGC Set point

What this curve shows is, assuming the waveform is Gaussian distributed (an important assumption, otherwise the upper portion of the curve showing the contribution of clipping noise changes), for an 8 bit real (single) ADC with full scale at 0.25V, is -12 dBFS (DC) which means -9 dB below a full scale sine wave. Full scale DC is at 0.25V, so the rms level of the waveform, if Gaussian distributed would optimally be at $(0.25)10^{(-12/20)}= 15.8$ mV rms, resulting in an additional noise due to the quantization that is about 40 dB below the overall power of the waveform, considering the total power across the full Nyquist bandwidth.

Here are some important points and considerations:

Actual Full scale is where spurious free dynamic range is optimized and that is typically 1 to 2 dB below actual full scale.

The "Equivalent Number of Bits" (ENOB) from the datasheet for the specific operating conditions is what should be used as the predictor of quantization noise and for the number of bits given in the chart above, not the actual number of bits the A/D converter provides.

Quantization noise is well approximated as a white noise evenly distributed across the first Nyquist zone as predicted by $SNR = 6.02 \text { dB/bit} + 1.76 \text { dB}$ for a full scale sine wave, where "bits" is from ENOB. This means we can reduce the noise in a resolution bandwidth of the measurement through subsequent averaging. However practical ADC's will also have spurs and specified on the datasheet under specific operating conditions as "Spurious Free Dynamic Range". The power level for a spur within a resolution bandwidth will not change as that bandwidth is reduced (as long as that bin is centered on the spur). Since the specific frequency range for spurs can be waveform dependent and difficult to predict, I consider that level the floor as to how low the noise can be through averaging.


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