Resolution after Oversampling, Filtering-Decimation

Question

The ADC I am working on has a resolution of 24 bits and a Signal-to-Noise and Distortion (SINAD) of 108.4 dB. Assuming only quantization noise is present, the Signal-to-Noise Ratio (SNR) of the ADC should be 146.24 dB. However, due to factors such as thermal noise and Total Harmonic Distortion (THD), the ADC cannot achieve this SNR, and the Effective Number of Bits (ENOB) is degraded to around 17.7 bits out of the 24 bits.

To enhance the ENOB, I plan to implement oversampling, which appears to improve the quantization SNR by adding the 10log(Fos/Fnyq). I want to quantify this improvement in terms of the total noise of the ADC, assuming the base value is 108.4 dB.

For instance, if I apply an oversampling rate of 256, then there should be a gain of 24.08 dB in the SNR due to oversampling. However, I'm unsure how this improvement is reflected in the total SNR of 108.4 dB. Will it be improved to 108.4+24.08=132.48 dB? After this, would it be possible to enhance the ENOB to around 21.7 bits theoretically?

Considering a filtering process after oversampling, how do I decide the length and scaling of the measurements at the output to leverage oversampling? In tools like MATLAB's FIR filter design utility, I can select to maintain full precision at the output or use a reduced bit length (e.g.24 bits), assuming 24-bit coefficients for the filter.

If I keep the full length of the accumulator, how is the improvement in the SNR reflected in the filtered results? Can I use just 29 bits out of the result of a 54-bit accumulator? How can I interpret this 29-bit quantity as a meaningful voltage value? Is it sufficient to use 24 bits again as an output, theoretically confining the error in my measurements to the missing bits based on the achieved ENOB after oversampling?

Answer 1

You don't know enough.

There's two absurd extremes: first, you could have an ADC that has no thermal noise at all, but distortion that's 108.51dB below the ADC's full-scale input range; second, you could have an ADC that has no distortion at all, but thermal noise that's 108.51dB below the ADC's full scale input range.

In the first case, oversampling and averaging won't do you any good at all -- a hypothetically zero-noise ADC with distortion and quantization noise, when fed by an equally hypothetical zero-noise signal, will have a perfectly steady output, and there won't be any remaining error to average out.

In the second case, there's no amount of oversampling and averaging that won't be better than less: you'll always gain 3dB of noise reduction each time you double the number of samples that you take, and average, at every step. In this case, oversampling by 256 and averaging would, indeed, bring the SINAD down by 24 bits.

I suspect that your actual case is somewhere in the middle, tending toward distortion-limited. If the SINAD figure could be improved by sampling over a longer interval, then the manufacturer would have an option bit to set on that ADC to slow it down and get better precision, or they'd have a closely-related part number that did so.

Answer 2

Your calculations are correct. Of course using an over-sampling factor of 256 will reduce the bandwidth of your converter by the same amount. Note that oversampling only improves the SNR if the ADC thermal noise is significantly larger than an lsb of the output word, which is true in your case.
Regarding the FIR implementation, it sounds like you are planning to use a 24-bit DSP with a 56-bit accumulator, is that correct? If so, then the top 8 bits of the accumulator are provided to handle overflow. If you would like to keep only 24 bits, then you should check for overflow before taking bits (47:24) as your result. If an overflow condition exists, you can substitute the appropriate limit.