Convert analog to digital and back to analog

Question

I'm trying to convert a signal from analog to digital and back to analog to observe the working of ADC and DAC, I use AD9248 as ADC and AD9767 as DAC, both of them are available on THDA ADA Altera board. I use the same clock for both DAC and ADC but I got nothing on the DAC output. The data output of ADC go inside an FPGA target and it give back the same data when clock edge to DAC. Here is my verilog code! Can someone tell me that it is even possible I receive a similar signal as the input at output?

module dac_adc(
               input wire         i_master_clk,
               input wire [13:0]  i_adc_data,
               //ADC
               output wire        o_adc_clk_a, // PLL clock input for ADC
               output wire        o_adc_clk_b, // PLL clock input for ADC
               output wire        o_adc_enable_signal_a, // ADC_OEA output enable pin for channel A
               output wire        o_adc_enable_signal_b, // ADC_OEA output enable pin for channel A
               output wire        o_adc_power_on, // POWER_ON pin, need to set it = 0 to enable both channel A and B
               // DAC
               output wire        o_dac_clk_a, // PLL_OUT_DAC1
               output wire        o_dac_clk_b, // PLL_OUT_DAC2
               output wire        o_write_signal_dac_a, // DAC_WRTA use the same signal with clock
               output wire        o_write_signal_dac_b, // DAC_WRTA use the same signal with clock
               output wire        o_mode_select, // DAC_MODE, mode select for DAC DAC_MODE = 1 is dual port, = 0 is interleaved
               output wire [13:0] o_dac_data 
               );
   wire                           w_analogclk;
   wire                           w_adc_enable_a = 0;
   wire                           w_adc_enable_b = 0;
   wire                           w_adc_power_on = 0;
   wire                           w_mode_select = 1;
   reg [13:0]                     r_adc_data;
   // connect master clock = inner wire
   assign w_analogclk = i_master_clk;
   // set mode for ADC
   assign o_adc_enable_signal_a = w_adc_enable_a;
   assign o_adc_enable_signal_b = w_adc_enable_b;
   assign o_adc_clk_a = w_analogclk;
   assign o_adc_clk_b = w_analogclk;
   assign o_adc_power_on = w_adc_power_on;
   // set mode for DAC
   assign o_mode_select = w_mode_select;
   assign o_write_signal_dac_a = w_analogclk;
   assign o_write_signal_dac_b = w_analogclk;
   assign o_dac_clk_a = w_analogclk;
   assign o_dac_clk_b = w_analogclk;
   // each data in and out in each clock edge
   always @(posedge w_analogclk)
     r_adc_data <= i_adc_data;

   assign o_dac_data = r_adc_data; // assign output of ADC = input of DAC
endmodule

Answer 1

You should certainly expect to see a similar signal with the following considerations:

The A/D converter must have an anti-alias filter in front of it to select the "Nyquist Zone" of interest. If undersampling a higher Nyquist Zone, also be sure that the A/D converter has an analog input bandwidth that exceeds the spectral occupancy of the signal. Distortion due to sampling clock jitter will be more pronounced when undersampling as well, so undersampling will impose a tighter restrction on the purity of the sampling clock.

The D/A converter will typically be implemented as a zero-order hold, and as such will impose a sine(x)/x response on the reconstructed signal. Additionally you will need an anti-imaging filter after the D/A to select the Nyquist Zone of interest, and the same considerations are given to the analog output bandwidth of the D/A as mentioned above for the A/D. Because of the sine(x)/x roll-off it is less common to reconstruct to higher Nyquist Zones.

Other posts I have made providing more details to what is introduced above are linked below:

Higher order harmonics during sampling

Where should I set my anti-aliasing filter corner frequency for this signal?

Sample and Hold Circuit at Digital to Analog Converters

D/A converter with