2
$\begingroup$

I'm using a Xilinx FPGA (Virtex) with 4 DDS cores (each supplied a 250MHz clock) used in parallel to provide a samples to a DAC38J82IAAV from TI, 16 bit DAC running at 1 Gsps. The four cores super sample (interleave their samples) to provide samples at 1 Gsps (250MHz clk * 4 cores = 1 Gsps) for the DAC. I'm trying to output frequencies between 20MHz and 500MHz with the DAC.

The DDS cores are configured in rasterized mode with modulus of 10000. I set the Phase Increment (PINC) to be (desired_freq * 10000)/250 and the Phase offset for each core to be 0, PINC/4, PINC/2, 3*PINC/4.

This works great for generating frequencies above 250MHz, but for frequencies below 250MHz, I see harmonics at Fout, 2*Fout, 3*Fout and so on. I would expect to see harmonics at Fout, Fsample-Fout, Fsample+Fout and so on, which I do see for frequencies above 250MHz.

Why am I seeing multiple harmonics at Fout interval for frequencies below 250MHz?

$\endgroup$
0
$\begingroup$

How high are your harmonics?

They are probably frequency spurs caused by the limited precision of your DDS.

https://www.analog.com/media/en/training-seminars/tutorials/MT-085.pdf

They could also be caused by the analog electronics, i.e. the DAC itself, the power supplies, etc.

Try generating a frequency that has a period not equal to a whole number. If the spurs dissapear, it's probably your DDS. IIRC, there are probably some options in the Xilinx and Altera DDS cores to attenuate the spurs.

$\endgroup$
  • $\begingroup$ Intended Fout is 250MHz and I'll see harmonics at 0MHz, 500MHz, 750MHz. Similarly if I choose Fout of 200MHz, I see harmonics at 0MHz, 200MHz, 400MHz. Bascially just integer multiples of my intended frequency, but my power level at Fout is still the strongest. If I change Fout in 1 Hz steps I will see the power level of the harmonics decrease as I approach 250MHz (the clock rate of my individual DDS cores and the clock rate of my DAC). $\endgroup$ – Mark73 Oct 14 '19 at 23:30
  • $\begingroup$ 1 - Try changing the rounding mode if possible. 2 - Try to add phase dithering (should be a core option) 3 - Change the frequency to something like 249.8 MHz if you can... $\endgroup$ – Ben Oct 15 '19 at 3:19

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.