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Technical Background

I'm making an audio processing board with an onboard microcontroller that takes in data via I2S from an ADC, applies digital filters, and outputs a stream of the same samplerate via I2S to a DAC. I plan to use DMA with double buffering/ping-pong buffering, wherein I receive one interrupt once a buffer has been filled with new data (and thus requires a new empty buffer to keep receiving data), and one interrupt when one has been sent (and thus requires a fresh buffer of processed data).

Herein lies the problem: the ADC and DAC are connected to separate I2S peripherals/blocks on the chip, so while both transmit data of the same word length and at the same samplerate, the "phase shift" between the input and output interrupts is in theory completely random (due to the runtime of each block's initialization code, and I do not know if the two blocks share a clock PLL). The spacing of the interrupts that provide more input and request more output can vary, varying the processing time I have in between.

Question

What is the established way to deal with unsynchronized (different phase, data rate or both) input and output channels when doing DSP on general-purpose microcontrollers? This isn't really an I2S-specific or platform-specific question, but a software one. How can I handle this situation in my code such that I am guaranteed a certain amount of time to process my data, while also minimizing total end-to-end delay?

I have considered delaying output by one interrupt, but this would introduce one buffer length of delay and still would have an extra random delay.

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You're already planning to use Direct Memory Access (DMA) with double buffering, which is a good start. You might be able to manage the phase shift by carefully managing your interrupt handlers, ensuring that they can handle incoming data quickly enough to avoid overflows or underflows.

If you have enough processing power, you might consider implementing an SRC (Sample Rate Conversion) or ASRC (Asynchronous Sample Rate Conversion). This would allow you to handle differences in sample rate and phase in a flexible and precise way. However, this could be complex to implement and might introduce additional latency.

If latency is a major concern, you might want to consider whether it's possible to synchronize the clocks of your ADC and DAC. This could greatly simplify the problem and reduce the amount of buffering and processing required.

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  • $\begingroup$ The ADC and DAC's master clocks could be shared, but the time each takes to begin transmitting/receiving data will still be different and arbitrary. Are ASRCs commonly implemented in this type of situation? There doesn't seem to be a lot of discussion about them $\endgroup$ Jul 24, 2023 at 0:35

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