I am trying to design the Symbol timing recovery (STR) block of DVBS Receiver.
In some literature they are given as $B_nT_s= 0.005$, $\zeta = \frac{1}{\sqrt 2}$, while in others it is given as $B_nT_s= 0.05$, $\zeta = 1$.
How should I proceed for choosing the $B_n$ and $\zeta$?
Should $B_nT_s$ factor change as we change $T_s$ (say from $0.1$ to $10^{-5}$ sec)?
There is an optimum loop BW that maximizes the SNR, and this applies to both Symbol Timing Recovery as you inquire about as well as Carrier Recovery. The specific answer depends on the characteristics of the noise source involved in your system, such as clock jitter and phase noise, and the modulation you are using; specifically how the signal energy is distributed in frequency. Without knowing those an exact answer cannot be determined, but I can at least share some insights from my own experience with it.
To state generally, I have found that the optimum loop BW to usually be somewhere between R/100 and R/20, where R is the symbol clock rate being recovered. I start with a value in this range and then through simulation with a valid noise and waveform model (or lab measurement) determine the actual optimum using SNR metrics vs Loop BW setting.
As for damping factor, I also start with a damping factor of 0.5 and then through evaluation using a step or impulse response test adjust for possible ringing due to parasitic delays that may be present in the loop.
In addition to the SNR considerations given above, there are also acquisition time constraints or possible dynamic noise conditions that would also motivate you to have as fast of a timing loop as possible: The faster the loop, the faster the acquisition time, and recovery time from an interference event, or the ability to track a highly dynamic change if it exists. There may also be waveform specific constraints such as the duration of a header in a packet based waveform used to establish timing. However as the BW for the tracking loops increase beyond a significant fraction of the timing symbol clock rate (such as >R/20), tracking errors will start to dominate the noise in SNR, since the loop will start to track out the modulation of interest.
To explain further from the perspective of a trade of Loop BW and SNR, the Loop BW sets the boundary at which your recovery loop will track timing noise (jitter/phase noise) in your signal. Timing noise has components at all frequencies (such as that viewed with a phase noise spectral density), and the lower frequency components of the timing noise (the change in zero crossing locations that is moving very slowly) will be tracked by the timing loop, and therefore suppressed. However the higher frequency components will not be tracked by the timing loop and therefore remain and contribute to noise as part of SNR. The timing loop can be viewed as a high pass filter on the jitter/phase noise components, passing the higher frequency components (including the modulation signals) and supressing the lower frequencies at a rate depending on the order of the loop. Thus you see the motivation to make the timing loop as fast as possible in the interest of tracking out as much timing jitter as possible. However, some of the signal energy of interest will be part of the "noise" being supressed by the timing loop; and this can be quantified by understanding the spectral characteristics of the modulation used. As the loop BW increases, too much signal energy is also removed, and thus it is clear how there can be an optimum setting for the Loop BW that maximizes SNR.
This hopefully provides insight into the approach and what to look for in the development of the system. In conclusion, I set the Loop BW as fast as possible (typically in the range of R/100 to R/20 where R is the symbol rate) while monitoring through simulation with accurate noise and waveform models the SNR metric; and either choose the point of best SNR, or if other factors such as acquisition time or more stringent dynamic conditions are involved, maximize BW without going below a target SNR metric.
