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enter image description hereI have done my receiver design with QPSK modulation. I am trying to communication between two systems at L band. My data rate is 1 Mbps. As my data rate is high I have allocated 64 bit for timing recovery.

Timing recovery has farrow interpolation filter followed by Gardner timing recovery, loop filter (2nd order) and interpolation control for the farrow interpolation filter. I am doing 2 samples/symbol analysis.

What I am assuming is the fractional value to the interpolation filter will stabilize once 64 bit allocated for timing recovery is over. But what I observe is the fractional value varies even after the 64 bit allocated is over because of which my data sometimes is wrong.

  1. can the fractional input to the interpolation filter vary?
  2. if yes why is the data sometime is wrong even if it is just direct board to board communication?
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  • $\begingroup$ Please give more details about the 64 bit sequence. Are these known values? Have you mapped them to appropriate constellation (BPSK/QPSK) ? Did you try eliminating carrier frequency/phase offset before attempting timing recovery? $\endgroup$
    – jithin
    Commented Mar 9, 2020 at 7:23
  • $\begingroup$ it is 01010101...... for I and Q data. well i am trying DQPSK so i am not using carrier reecovery. $\endgroup$
    – mark
    Commented Mar 9, 2020 at 8:51
  • $\begingroup$ @mark that's the worst possible preamble! $\endgroup$
    – Marcus Müller
    Commented Mar 9, 2020 at 12:07
  • $\begingroup$ @MarcusMüller For consideration of timing recovery alone, I would say that is the best preamble. If needed for packet synchronization, I would agree it is a bad choice. $\endgroup$
    – Dan Boschen
    Commented Mar 9, 2020 at 12:24
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    $\begingroup$ @DanBoschen I had to read mark's comment twice; I first thought that was a bitstream, in which case it'd have always been the same QPSK symbol (the one mapped to bits 01), and that would have indeed not have been a good sequence. But you're right, this ensures transitions, so it's great for timing recovery. $\endgroup$
    – Marcus Müller
    Commented Mar 9, 2020 at 13:34

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As far as the recovery time and results for the timing recovery, this is a loop implementation and you would need to review the complete loop for stability and gain parameters to balance loop bandwidth & convergence time, stability and noise performance.

Even with direct board to board communication you will have a static timing offset as the receiver needs to determine the optimum point in which to sample the recovered data in each symbol.

Step response testing of the timing error at your loop filter input and output can be insightful; the input to the loop filter will likely be quite noisy but you can filter your observation (as long as the filter bandwidth is much wider than your expected loop bandwidth this will be valid) to be able to see how it responds to a step change in time offset. Even better is if you have an accurate simulation model of your receiver so that you can observe the time offset more directly, and to observe what occurs as you change loop gain parameters.

Also through simulation and with testing on your hardware I would recommend creating an eye-diagram to better understand the core problems you may be having with data recovery. With this you can best observe the predicted sampling location for making a data decision versus the ideal.

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  • $\begingroup$ Thanks a lot for a very quick response. So my timing recovery should recover in the 64 bits allocated. after that it should be stable for the rest of the frame? So if changing after 64 bits then i have to see the loop filter. is that right? step response testing means giving step signal to only the loop filter? what inference can i get $\endgroup$
    – mark
    Commented Mar 10, 2020 at 3:55
  • $\begingroup$ My concern is if you haven’t designed it as a control loop then the loop bandwidth may not be properly set in which case it could be much too slow (not converging in time) or possibly unstable. There is no way to know this from what you wrote, but if you do what I suggested and post those results we may be able help further. $\endgroup$
    – Dan Boschen
    Commented Mar 10, 2020 at 11:20
  • $\begingroup$ Hi Dan, I have attached image . I am giving step response to the loop filter and output is shown in the image. loop bandwidth is 0.002. $\endgroup$
    – mark
    Commented Mar 11, 2020 at 6:28
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    $\begingroup$ I can’t make sense out of your step response but 1/500th is the symbol rate is much to slow—— it would take approximately 1000 symbols or more to converge! I think 1/20th to 1/50th should be adequate. $\endgroup$
    – Dan Boschen
    Commented Mar 12, 2020 at 4:47
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    $\begingroup$ It would be helpful if you could label your axis and would be helpful to label your x axis in units of symbols. I don’t understand why you would have such a big step after it seems to converge in the top plot. This will be much more detailed than we can really proceed with here (into the the weeds of the design details and we will end up putting a lot more comments here than the system likes)- but I suggest making a super long preamble just for testing of that settling time and also developing an actual system model of your loop to see the intact of all those gain parameters. $\endgroup$
    – Dan Boschen
    Commented Mar 12, 2020 at 12:13

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