Consider the controlled dynamical system $\dot{x}_t = f(x_t, u(t-\tau_{sd}))$, where $0<\tau_{sd}$ denotes the time delay caused by sampling. It is intuitively clear that the time delay caused by sampling is a function of the sampling time interval $T_s = \frac{1}{f_s}$, where $f_s$ is the sampling frequency, that is $\tau_{sd} = \tau_{sd}(T_s)$ and that $\tau_{sd} \leq T_s$. Assuming that computing the control takes half the sampling time interval and presumably based on real-world experience, we can approximate that $\tau_{sd} \approx \frac{T_s}{2}$ as stated in the notes at this link by @TimWescott who is a contributor on the platform dsp.stackexchange.com.
In the process of designing the controller, clearly we should choose the sampling frequency to be higher than the Nyquist sampling frequency $2f_{sys} < f_s$, where $f_{sys}$ denotes the highest frequency of the system, so that $$\frac{1}{f_s}=T_s < \frac{T_{sys}}{2} = \frac{1}{2f_{sys}},$$ where $T_{sys}$ denotes the shortest time period associated with the system. In the case that we choose $f_s = f_{sys}$, the associated phase delay caused by the sampling delay at the frequency $f_s$, based on the first order time delay (FOTD) model $\mathrm{e}^{-s\tau_{sd}}$, would be $$\omega_{sys} \cdot \tau_{sd} = 2\pi f_{sys} \cdot \tau_{sd} = 2\pi f_{sys} \frac{T_s}{2} = 2\pi f_s \frac{T_s}{2} = \pi = 180^{\circ},$$ where $\omega_{sys} := 2\pi f_{sys}$. However, if we choose $f_s = 10\cdot f_{sys}$, then the phase delay associated with the sampling time delay based on the FOTD model at the frequency $f_s$ is $$\omega_{sys} \cdot \tau_{sd} = 2\pi f_{sys} \cdot \tau_{sd} = 2\pi f_{sys} \frac{T_s}{2} = 2\pi \frac{f_s}{10} \frac{T_s}{2} = \frac{\pi}{10} = 18^{\circ}.$$ Therefore, the rule of thumb prescribed in the notes at the link provided earlier is to apply a sampling rate of $10$ or $20$ times the desired bandwidth of the controller.
Is there a cleaner way of arriving at the approximation $\tau_{sd} \approx \frac{T_s}{2}$ used in the line of reasoning above? Further, are there any other critical issues which are not addressed in the design logic stated?