# Effects of delay in a discrete-time controller for a continuous-time plant

I'm trying to understand the effects of sample-to-update delay in digital control of power electronics. I am aware of the issue but not 100% sure how to quantify it. There is an interesting paper by Böcker et al, On the Control Bandwidth of Servo Drives, which includes this diagram:

The time delay is characterized by $$T_{\Sigma,I}$$ as shown in four cases.

(NOTE: This is an averaged-model current-control loop in a three-phase motor drive. Please ignore any nonlinearities for the purposes of answering this question.)

Case d shows a computation delay of zero (impossible in practice, but we can come arbitrarily close to it with fast FPGAs) where current is digitized and a PWM duty cycle immediately updated to hardware. The delay $$T_{\Sigma,I} = 0.5T_c = 0.25T_s$$ (the article has a typo and states $$0.5T_s$$) where $$T_c$$ is the PWM update and control loop sampling rate of half of the PWM period $$T_s$$. (Cases a and b have $$T_c = T_s$$; cases c and d have $$T_c = \frac{1}{2}T_s$$.)

In all cases, the delay is stated as equalling the computational delay plus half of the PWM update time $$T_c$$ --- which they state as the sample/hold time, having a transfer function of $$(1-e^{-sT_c})/sT_c$$.

My question is, why is this half of the PWM update time? Why doesn't it also consider the delay until the next input ADC sample?

On the one hand, I get it: the change takes effect right away (we'll neglect the impact of PWM carrier harmonics; that would depend on the duty cycle and when the transistors switch) but occurs over the full time $$T_c$$, so the average delay is $$T_c/2$$.

But on the other hand, it would seem to me that the total delay should be the sample-to-update time, which is the computational delay plus the time between the PWM update (when the output starts to change) and the next digitized sample (when the digital controller sees it), which in these four cases would be:

• a. $$2T_s$$
• b. $$T_s$$
• c. $$T_s$$
• d. $$T_s/2$$

This is a different amount than the paper states.

If it helps, consider the plant transfer function from voltage to current as an inductive load $$1/Ls$$ rather than something more complicated, so the change in current $$\Delta I$$ sensed at the end of any control period $$Tc$$ is $$\Delta I = VT_c/L$$ where $$V = DV_{dc}$$ (D is the duty cycle output of the controller and $$V_{dc}$$ is the DC voltage source; conceptually these can be lumped together and considered as a controller output $$V$$)

So I guess what my question is, stated rigorously, is that if the controller's transfer function in the Z-domain is $$C(z)$$, how do we model the system for stability analysis?

What I think is the case is that in these four cases, we can model the entire plant $$G(z)$$ as:

• case (a): $$G(z) = G_0 z^{-1} \frac{z^{-1}}{1-z^{-1}} = G_0 \frac{z^{-2}}{1-z^{-1}}$$ where $$G_0 = T_c/L$$ --- the $$z^{-1}$$ is the computational delay and $$G_0 \frac{z^{-1}}{1-z^{-1}}$$ is the response of the PWM and inductive load effectively acting as an integrator over time $$T_c$$

• case (b): $$G(z) = G_0 \frac{z^{-1} + z^{-2}}{2(1-z^{-1})}$$ --- the integrator acts on the average of the command from the previous cycle $$V[k-1]$$ taking effect in the first half of the control period, and the command from the current cycle $$V[k]$$ taking effect in the second half of the control period

• case (c): $$G(z) = G_0 z^{-1} \frac{z^{-1}}{1-z^{-1}} = G_0 \frac{z^{-2}}{1-z^{-1}}$$ --- same as case (a), but with $$T_c = T_s/2$$ this time

• case (d): $$G(z) = G_0 \frac{z^{-1}}{1-z^{-1}}$$ --- same as case (c), but with no computational delay

If I use the bilinear transform with $$z \approx \frac{1-sT_c/2}{1+sT_c/2}$$ then I get (after simplification, and convincing myself I can morph time delays as $$1-sT_c/2 \approx e^{-sT_c/2}$$):

• case (a): $$G(s) \approx G_0e^{-sT_c}\frac{1-sT_c/2}{sT_c} = e^{-sT_c}(1-sT_c/2)\frac{1}{sL} \approx \frac{e^{-3sT_c/2}}{sL}$$ (with $$T_c = T_s$$)

• case (b): $$G(s) \approx G_0\frac{e^{-sT_c}}{2}\frac{1}{sT_c/2} = e^{-sT_c}\frac{1}{sL}$$

• case (c): $$G(s) \approx G_0e^{-sT_c}\frac{1-sT_c/2}{sT_c} = e^{-sT_c}(1-sT_c/2)\frac{1}{sL} \approx \frac{e^{-3sT_c/2}}{sL}$$ (with $$T_c = T_s/2$$)

• case (d): $$G(s) \approx G_0\frac{1-sT_c/2}{sT_c} = (1-sT_c/2)\frac{1}{sL} \approx \frac{e^{-sT_c/2}}{sL}$$ (with $$T_c = T_s/2$$)

namely an integrator with effective delays of $$1.5T_s, T_s, 0.75T_s, 0.25T_s$$ respectively. (which is exactly what the paper's diagram indicates)

Is this analysis correct? How should I think about these delays?

• In a few years, SiC mosfets will replace IGBTs in most applications. This will allow designer to increase the PWM frequency and reduce the effective delay. – Ben Sep 4 '20 at 21:17
• @Ben that's not the point; I'm trying to understand the signal processing implications. Anyway, it's unlikely that SiC will take over completely anytime soon. Si MOSFETs and IGBTs took years to displace BJT power transistors. Until SiC becomes cost-effective and some of the secondary issues resolved (at a seminar in IEMDC last year there were some interesting concerns about manufacturing defects because of the wafer-growing process), Si will be around for a while. – Jason S Sep 7 '20 at 18:50

My question is, why is this half of the PWM update time? Why doesn't it also consider the delay until the next input ADC sample?

You answered this yourself -- it's the effective, average delay.

So I guess what my question is, stated rigorously, is that if the controller's transfer function in the Z-domain is C(z), how do we model the system for stability analysis?

The paper is behind a paywall, so I didn't read it. But it's controlling a PWM drive to a motor or coil or something. That means that if you're concerning yourself with cycle-by-cycle differences, the system is nonlinear -- and very possibly nonlinear enough that you can't use linear analysis to analyze it.

If you can use linear analysis to analyze it, you'd probably want to linearize the system around several different operating points (probably, based on what I know about switching power supplies, it would be sufficient to linearize around operating points that demand various duty cycles -- see below -- without having to investigate the entire state space of the system).

In fact, there's a well-known nonlinearity prevalent in cycle-by-cycle current mode power supplies that causes a sub-harmonic oscillation at 1/2 the switching frequency, whenever the duty cycle of the PWM exceeds 50%. This must be overcome with something usually called "slope compensation", which linearizes and stabilizes the inner current loop. You can find papers on this phenomenon (many of them written by Unitrode, now TI), that may inspire your own analysis and understanding.

• In my experience, modelization errors such as parasitic capacitances and non-linearities (inductor saturation) are the biggest performance limiters... Unless your PWM frequency is really low. – Ben Sep 4 '20 at 21:19
• What size inverters are you used to working on (since you mention IGBT's elsewhere). Certainly for the Unitrode controllers, treating the inductor as linear for the purpose of slope compensation worked pretty well. But that's for a population that would treat a 500W inverter as OMG big. – TimWescott Sep 4 '20 at 23:43
• In my case, 10kW and over inverters. We drive non-linear loads and the peak current in the inductors can get really high even if the RMS current is not. – Ben Sep 5 '20 at 15:47
• I should have mentioned -- assume that linearity applies, and an average model can be used. The nonlinearities are generally not relevant. – Jason S Sep 7 '20 at 18:53
• "In fact, there's a well-known nonlinearity prevalent in cycle-by-cycle current mode power supplies that causes a sub-harmonic oscillation at 1/2 the switching frequency, whenever the duty cycle of the PWM exceeds 50%" -- this is outside the scope of my question, but it doesn't apply to motor drives that use average-model current control with three-phase bridges. We don't use cycle-by-cycle control. – Jason S Sep 7 '20 at 18:58