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Digital PLL loses lock every time mesage crosses zero

You are having trouble because that's not a Costas loop. A Costas loop uses demodulated data in some form to change the phase that's expected from the signal. You're just taking the I/Q demodulate …
TimWescott's user avatar
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Costas Loop SNR

$N_0$ is the noise spectral density at your PLL input. $B_n$ is your PLL bandwidth. $P_{in}$ is the power of the signal being received. If you work out the units, all the Watts and Hz and whatnot w …
TimWescott's user avatar
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5 votes

Why is phase range between $-\pi$ and $+\pi$ (instead of $0$ and $2\pi$)?

First, when you're talking angles, in DSP pretty much all angles are $\mod 2\pi$. So $2\pi \equiv 0$. Usually it's more convenient to keep angles on the interval $\left [-\pi, \pi \right )$, because …
TimWescott's user avatar
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Symbol Sync blocks in GNU Radio seem to use PID (well, PI) for their clock sync feedback loo...

Keep in mind that we are talking about a clock synchronization loop, so you need to think of the behavior from a control-systems perspective. FIR Just discard that notion right out. …
TimWescott's user avatar
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