I have succesfully modeled a modem using floating-point data and with the following scheme, where the SRRC filter has gain G=6dB.
Modulator -> SRRC(UPx4) -> D/A -> Channel -> A/D -> AGC -> SRRC(DOWNx2) -> Remaining receiver blocks
The modulator outputs full-scale (-1 to +1) I/Q values and at the receiver I'm getting a signal whose power is 1/4=0.25W as expected, the digital AGC uses that value as target, and after the other filter I do get back a more-or-less unitary-energy signal. The reason to keep the ADC there is to provide the other blocks (e.g. Gardner synchronizer) with a signal whose amplitude is almost unitary.
Now, I'm not sure this is the best way to structure the TX/RX chain but I'm pretty sure this set-up won't fly that well when converted to fixed-point arithmetic: what I'm afraid of is that the AGC/SRRC combination as devised may cause the signal to clip/overflow and thus degrade the receiver performance. Is there a better and perhaps wiser way of designing the receiver chain? Use normalized filters? Use a different target value for the AGC?
The bit-growth caused by the two SRRC filters doesn't worry me, the plan is to compute the result with higher precision and then round/truncate it to 16-bit.
I'm also considering to lower a little the AGC target level, instead of targeting 1/4 of the quantized power scale the reference could be moved to a smaller value (e.g. 1.25) and reduce the chances of clipping.
I'm pretty new to all this DSP stuff so please bear with me, I'm trying to learn as much as possible while also trying to get a product out of the door :)