# How can I experimentally find the bandwidth of my PLL?

I recently designed a phase-locked loop. I would like to quantify its bandwidth so that I can better understand it.

However, I made this bandwidth in an informal manner due to my lack of formal education on the topic. Is there an experimental way for me to find the bandwidth of this system?

My PLL uses a dual-channel lock-in amplifier as a phase detector, a PI controller as a loop filter, and the system is digital (on an FPGA embedded system).

• Please post a block diagram
– Ben
Mar 6 '21 at 2:54
• By the way, as far as I read this, you could derive the bandwidth from how you designed the PI, so that'd be my way to go instead of "measuring" it. Mar 6 '21 at 14:07
• @MarcusMüller measuring it is a good validation procedure IMO; especially with a digital implementation it is easy for someone to forget the factor of T etc. I typically do this on every loop I implement in hardware (or even confirming analog variations) Mar 6 '21 at 16:51
• I will try to post a block diagram later today or tomorrow Mar 6 '21 at 16:58

A step response test is an easy way to determine the bandwidth. Sum a small step into the control voltage of your oscillator (VCO or NCO), and measure the 90% to 10% fall time of the corrected response at the output of the loop filter as shown in this block diagram. Note that the loop will respond in such a way to completely cancel the injected offset, but can only respond at a rate within its bandwidth. Given this is in an FPGA implementation, this would be an easy test feature to have permanently included, especially valuable if this is a mixed signal system with external analog components that may vary from unit to unit or over temperature.

The bandwidth is given by the following approximation (this is accurate for a first order loop but will provide a reasonable estimate for higher order loops as well):

$$BW = \frac{0.35}{t} \space\space\space\space \text{(first order system)}$$

Where $$BW$$ is the 3 dB bandwidth in Hz and $$t$$ is the 10%/90% rise or fall time. This equation comes from solving the first order response equation given by $$y(t) = e^{-t/\tau}$$ where $$\tau$$ is the reciprocal of the bandwidth in radians/sec. For second order loops with a typical damping factor of 0.7 this relationship is closer to:

$$BW = \frac{0.33}{t}\space\space\space\space \text{(second order system, damping factor = 0.7)}$$

You could use this test for further loop forensics such as damping factor, natural frequency and a more accurate estimate of the bandwidth through observation of the overshoot and ringing in the corrected response.

The step should be as small as possible to stay within the tracking range of the loop, but large enough to make a reasonable measurement of the response time.

Below demonstrates the accuracy of using this first order approximation on a second order system, showing the step response and frequency response of a generalized 2nd order system with a natural frequency of 1KHz where the damping factor was varied between .5 and 1.0. The dashed red lines indicate the 10% to 90% crossings for rise time and the -3 dB BW crossing for the frequency response.

The following table shows the resulting accuracy of the approximation versus actual 3 dB bandwidth for each of these cases.

• Thank you for the advice. I will look into implementing this method. Is there a way for me to measure the BW directly through the frequency domain? I'm curious due to the possibility of difficulty in measuring the elapsed time. Could I modulate a carrier signal in frequency then measure the output of it's amplitude through the PI? Mar 6 '21 at 17:04
• Yes you could do that. Ultimately if you are sweeping a sine wave you would be doing exactly what Tim is suggesting; just taking a few points to find where the signal drops by 3 dB. I find the step response approach quick and easy if you are fine with 10% accuracy; measuring the time to that precision is trivial. Mar 6 '21 at 17:11

This is just a different flavor of what Dan Boschen suggests. In fact, the actual summing junction part is exactly what he's suggesting.

Insert a summing junction, and then inject a signal ($$u_A$$ in my diagram). For more work, you can get the frequency response directly. If you inject a sine wave at $$u_A$$ while you pick off $$u_R$$ and $$y$$, you can let it run for a while, then determine the amplitude and phase of $$u_R$$ and $$y$$ relative to $$u_A$$.

You can take measurements at various frequencies, and directly build up a Bode plot of your system's response. If you express everything as complex numbers, then $$-\frac{Y(f)}{U_A(f)}$$ is your closed-loop response, $$\frac{U_R(f)}{U_A(f)}$$ is your system's sensitivity function, and $$\frac{Y(f)}{U_R(f)}$$ is the system's open-loop gain.

It is a pain to write the necessary code to do this; it's almost not worth it for just one project (then I'd probably do what Dan is suggesting). But if you're doing a lot of closed-loop stuff, particularly if there's physical components that can vary, or that are nonlinear, then it's a great time-saver when you spread it out over two or three projects.

(From Applied Control Theory for Embedded Systems, Tim Wescott, 2006, Elsevier/Newnes)

• Yes! @TimWescott this approach is actually great for detailed verification specifically to get the open loop Bode plot on a closed loop system, extracting actual gain and phase margin. I have done this using Stanford Telecom’s SR785 low frequency signal analyzer which takes away a majority of the pain you reference. The step response is a quick test but for final design verification I would recommend what you suggest here for sure - especially if analog factors are involved. Mar 8 '21 at 0:03