I want to use the AD7401 Sigma delta modulator connected to my FPGA.
The Datasheet pg.15 has some demo verilog code which I understand alright except one thing:
They use unsigned integers for all of the registers. Which means especially for the Integrators(that only get 0 or 1 added) that they will definately overflow at some point. The Integrators of CIC Filters are designed to overflow, but all the sources I found explicitly say that this requires twos complement to work properly. Am I missing something, or why does the Decimator work with unsigned Integrators aswell(that dont wrap around "nicely").
Also am I right that switching all the registers to signed, and mapping the IO Input (0,1) -> to First Integrator(-1,1) will fix this and result in a signed output.