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I'm quite new to the area so I need help to progress at some point.

Basically I have a signed 16 bit ADC which means it maps -10V to +10V range to 16 bit. So the max voltage +10V is 2^15-1 = 32767; zero is 0; and -10V is -2^15 = -32768.

I want to create/plot a sinusoid in MATLAB or Python where I can mimic exactly the ADC which samples a 1V 100Hz sinusoid input for 1 seconds which is sampled with 512Hz sampling rate. At the end I want to obtain the same FFT plot where I would obtain after a real ADC sampling.

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ADCs are devices which can be simplified to behave ideally but are actually not doing so due to their physical limitations. Hence if you would like to make a realistic simulation of ADCs, then you should seriously consider their physical charactheristics as well. Otherwise if you are ok with the ideal mathematical definition of their outputs then the following simple MATLAB/OCTAVE code implements an example uniform quantizer. Please be very careful with the concept of simulation when it comes to ADC and quantizers.

clc; clear all; close all;

% ANALOG SIGNAL:
T = 1;          % observaton interval in seconds
f0 = 5;         % input sine frequency in Hz.
Fs = 1000;      % sampling frequency in Hz.

t = 0:1/Fs:T;   % sampling instants time

A = 1.25;       % amplitude of the input sine wave.
ax = A*cos(2*pi*f0*t)-(1E-15);   % ideal analog signal simulated with 64 bit IEEE floating point format
ax(ax <= -A) = -A + 1E-14;       % slight conditioning on the input so that decision limits are maintained.

figure,plot(t,ax);
title('simulated analog signal in 64-bit binary64 format');

% ADC :
N = 3;          % number of bits of uniform, symmetric, midtreat quantizer.
M = 2^N-1;      % number of levels: odd
qx = (2*A/M) *  round( (M/(2*A)) * ax ) ;   % QUANTIZED... (simulated within 64 bit container format)

figure,plot(t,qx),
title('simualted quantized signal');

The input and output are as follows:

enter image description here

enter image description here

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  • $\begingroup$ but Fat, there really are a full M=2^N levels coming from a conventional N-bit ADC, one more than what you are saying. and with biasing and the like, strict symmetry is not really attainable and you may as well simply use the qx=(2/M)*floor((M/2)*ax); mapping for the quantizer. $\endgroup$ – robert bristow-johnson Jul 24 '18 at 1:41
  • $\begingroup$ @robertbristow-johnson . Yes that's right for sure, but I wanted to show a symmetric one. That requires an odd number of levels and hence throws out one level (inefficient at low bits). If you don't care for symmetric quantizer then for sure use 2^N levels... However even with the biasing (being very slight) the symmetry is quite attained compared to the step-size noise power, that already limiting the accuracy... $\endgroup$ – Fat32 Jul 24 '18 at 1:45
  • $\begingroup$ well, the only way to "throw out one level" is to, in your DSP software, map 0x8000 to 0x8001 which is the negative of 0x7FFF. but the 16-bit (in this example) ADC is still 2^16 levels. biasing and DC offset error and noise pretty much throw all of this hypothetical precision away. also, mid-riser instead of mid-tread, is symmetrical and uses all 2^N levels. $\endgroup$ – robert bristow-johnson Jul 24 '18 at 1:58
  • $\begingroup$ @robertbristow-johnson yes but a midriser does not have a black (zero) output... :-) $\endgroup$ – Fat32 Jul 24 '18 at 18:23

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