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Could anyone explain the action of interpolation control in symbol synchronization? What the underflows mean? And how it provides the fractional part? I know how other components work but don’t understand the process of interpolation control. I appreciate it if anyone could help me out.

Now my question is that the output of TED is the error difference between optimal sampling point and sampling points by ADC, why the output should plus 1/N and how this will control the interpolator. What the role of the modulo-1 register? Could anyone please give an numerical example?

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This is essentially a "Numerically Controlled Oscillator" (NCO) as detailed in this post, used in a timing recovery loop with a timing interpolator as detailed in this post, where the Look Up Table is simplified to be a square wave by using only the MSB of the counter output (as given by the underflow strobe which is the rollover condition where the MSB changes). This could be implemented and explained much simpler by using a modulo counter that cycles on overflow (for instance count to 7 in steps of 3 would be 0, 3, 6, 1, 4, 7, ...) and using the rising edge of the MSB as the "strobe"; notice if we change the step size (3 here) the rollovers will occur at a faster or slower rate and thus the recovered clock is adjusted. The reason for the separate strobe and not the MSB directly, as well as using the under flow to start the next count, may be due to the specific and less efficient implementation of the interpolator and counter. The second reference I provide above shows a very efficient and robust implementation based on using a polyphase filter structure as the interpolator and omits the need for the additional counter acting as an NCO (the counter shown in the 2nd link is the loop filter itself which can be easily modified for higher order and higher type loop implementations).

The TED is a timing error detector which then feeds into a loop filter which would in a control loop provide the equivalent "Frequency Control Word" (FCW) into the counter here as $v[n]$ which is then scaled by $N$. This control word adjusts the frequency of the square wave such to drive the error out of the TED to zero. The resulting square wave out of the counter represents the recovered "symbol clock" which due to the loop will be properly synchronized to the incoming data symbols as determined by the TED. If time synchronization was such that the local symbol clock was rising a little late, the FCW would increase momentarily increasing the frequency of the local symbol clock sufficient to bring the time edges together and then the FCW would return to be the same frequency as the incoming symbol rate, with no time offset. Similarly if time synchronization was rising too early, the FCW would reduce to lower the frequency of the symbol clock momentarily to bring the time edges together.

With that high level overview, please read the linked posts above which explains in detail how the counter creates a square wave frequency out of it's most significant bit and the implications of the fractional bit with the bottom line that this is a count controlled oscillator. (Output frequency of square wave is proportional to $v[n]$). To note, the second post provides significant detail on a full implementation using a Gardner TED and polyphase filter interpolation, but is a simpler approach of not using an NCO to recreate a timing clock but instead derive a relatively static time offset value from the output of the loop filter directly: the cyclical counter shown there is not generating a square wave but only changes its output up or down when a timing error exists.

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  • $\begingroup$ Hi, Dan, I looked through your link and other materials, but I still don’t understand how the control works, $\endgroup$
    – Xiang Li
    Commented Mar 9, 2023 at 6:49
  • $\begingroup$ I don’t understand why the error signal needs to add 1/N and what interpolator do when the modulo 1 action produces 0. $\endgroup$
    – Xiang Li
    Commented Mar 9, 2023 at 7:09
  • $\begingroup$ @XiangLi The $1/N$ is just a fixed gain adjustment inside the loop for stability. It sets the loop BW and would be specific to the sensitivity of the specific TED used and other gain constants within the loop. I am not sure how familiar you are with control loops but such a feature would be very specific to this particular implementation. More generally there would be something to set the gain of how big the change should be on each cycle which sets how fast or slow the loop responds. In most cases due to loop order or even parasitic delays the loop can be unstable if not set right. $\endgroup$ Commented Mar 9, 2023 at 9:57
  • $\begingroup$ The interpolator essentially increases the sampling rate on the waveform to higher precision, and the correct sampling event in time occurs when the modulo 1 action produces 0 (it is the timing clock). The precision is set by how close we really need to be to the "true" sample-- which is the essence of "Timing Recovery" which is what this is. $\endgroup$ Commented Mar 9, 2023 at 9:58

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