Practical wideband digital beamforming for large arrays in radar applications

Question

I do understand the mathematics behind digital beamforming but I am not sure how such systems are practically implemented. For example, in a typical wideband FMCW radar operating in S-band, the (baseband) pulse bandwidth can be as large as 500MHz. To digitize this signal, you need high-speed ADCs, typically 1GHz sampling frequency. As far as I know, these ADCs are not cheap.

Now, if you have let's say a Uniform Rectangular Array (URA) with 20 antenna elements, you need to replicate your RF frontend 20 times! This RF frontend typically will include an LNA, a mixer and the high-speed ADC.

In addition, the sheer amount of data produced by the above system is huge requiring large memory and processing power.

My questions are thus:

1. Does the above scenario reflect how practical beamforming systems are implemented or is it too naive? am I missing something fundamental here?
2. Are there any hardware/signal processing tricks that can help reduce the hardware or processing requirements in such systems?

Thanks

Answer 1

I've not worked on the design of such systems before, but I think your notions are on the money. Specifically, yes, beamforming arrays do have RF front ends that are replicated many times. The complexity of contemporary phased array radars is astounding in this regard; there are designs that have hundreds of individual antenna elements in them with impressive levels of control of the array response using various signal processing techniques.

And as you suspected, yes, this sort of approach is not cheap. Gigasample-class ADCs are available commercially in the few-thousands-of-dollars range, but it's possible that the custom, low-quantity RF front ends used in systems like this would dwarf that cost. Even so, radars with this sort of capability are often found as subsystems in very expensive larger systems (like a multi-hundred-million-dollar fighter jet).

As far as the backend digital signal processing goes, that's a pretty mature market that has developed over the past few decades. The main goal is processing density: getting the maximum number of FLOPS into the smallest volume. After all, such radars are often used in space-constrained applications like aircraft. Therefore, you'll see a lot of the processing done on custom FPGAs and/or single-board computers that can be stacked compactly into standardized chassis assemblies (like VPX or CompactPCI).

Answer 2

okay - I think the technique I was looking for is formulation of a synthetic aperture as in Synthetic Aperture Radar (SAR). The 'trick', in the general case, where static target and radar platforms are involved, would probably be that all the array elements will be physically present as opposed to conventional SAR where platform motion is used to synthesize a really large aperture. Using RF switching to simulate the platform motion, one can capture SAR data sequentially and apply well-known SAR techniques to achieve desired performance i.e. fine angular resolution.

The 'catch' in this case will be the extra time required for SAR data acquisition compared to a full-blown digital beamformer. Another one is that this technique can possible be valid for beamforming-on-receive-only scenarios.

Answer 3

As long as you have a customer who will pay the ASIC cost, that is about \$25m NRE design cost, you can get all 20 front ends, ADCs and digital beamforming arithmetic on one CMOS chip anywhere from DC to 100GHz for under \$20 recurring cost