I am currently studying the topic of oscillator phase noise in frequency modulated continuous wave (FMCW) radar. In my specific case, the radar is implemented on an FPGA (AMD RFSoC). Thus, the echo is directly digitized by the ADC after the antenna (and some filter and amp. stages, but no down mixing). Deramping will be done in the digital domain, followed by a digital filter and downsampling to reduce the memory demand.

Now I see a lot of studies on phase noise and radar, but usually they assume the deramping in the analog domain. I have been wondering whether I will get different effects with direct RF-sampling.

For example: The local oscillator used to synthesize the ADC and DAC sampling clocks will have some phase noise and maybe frequency drifts. This would lead to jitter and a sampling frequency drift as I understand. I have not encountered this in literature when the deramped signal is sampled by the ADC.

Now, assuming I receive the echo with an ADC that is driven by a different LO, the phase noise will not cancel out. My idea of an echo model (from point target) looks like this: $$ s_{rx}[T'_s n] = e^{j2\pi\left( f_0[T'_sn - \tau +\Delta t]+ \frac{\alpha}{2}[T'_sn - \tau +\Delta t]^2 \right)} $$ where $\tau$ is the travel delay, $f_0$ the start frequency (assumed perfect for simplicity), $\alpha$ the ramp rate, $T'_s=T_s(1+\epsilon)$ the sampling interval of the ADC that potentially deviates from the assumed ideal sampling interval $T_s$, $\Delta t$ the clock jitter and $n=0, 1, \dots, N$ the sample index.

The deramping would be done with an ideal stored chirp in memory (assuming the timing is synchronised) $$ s_{ref}[T_sn]=e^{j2\pi(f_0[T_sn]+\frac{\alpha}{2}[T_sn]^2)} $$

I have written out the outcoming beat signal ($s*_{rx}\cdot s_{ref}$), which gets pretty blown up. Especially when the time delay $\tau$ becomes time dependent due to movement.

EDIT: Here is the deramped signal (without movement) $$ \begin{align} s_{deramp}[n] = &s^*_{rx}\times s_{ref}\\ &e^{j2\pi\left( f_0(T_s-T'_s)n + \frac{\alpha}{2}(T_s-T'_s)^2n^2 \right)} \times\\ &e^{j2\pi\left(f_0(\tau-\Delta t) - \frac{\alpha}{2}(\tau^2-\Delta t^2) + \alpha (\tau-\Delta t)T'_s n + \alpha\tau\Delta t \right)} \end{align} $$ My question is:
Is this model correct or somewhat in the correct direction? Am I misunderstanding something? I am lacking the experience to judge if some of these effects are potentially negligible. If anyone knows resources I could read up about this, a tip would be greatly appreciated!

Hope the question is clear, otherwsie I clarify!

I am currently studying the topic of oscillator phase noise in frequency modulated continuous wave (FMCW) radar. In my specific case, the radar is implemented on an FPGA (AMD RFSoC). Thus, the echo is directly digitized by the ADC after the antenna (and some filter and amp. stages, but no down mixing). Deramping will be done in the digital domain, followed by a digital filter and downsampling to reduce the memory demand.

Now I see a lot of studies on phase noise and radar, but usually they assume the deramping in the analog domain. I have been wondering whether I will get different effects with direct RF-sampling.

For example: The local oscillator used to synthesize the ADC and DAC sampling clocks will have some phase noise and maybe frequency drifts. This would lead to jitter and a sampling frequency drift as I understand. I have not encountered this in literature when the deramped signal is sampled by the ADC.

Now, assuming I receive the echo with an ADC that is driven by a different LO, the phase noise will not cancel out. My idea of an echo model (from point target) looks like this: $$ s_{rx}[T'_s n] = e^{j2\pi\left( f_0[T'_sn - \tau +\Delta t]+ \frac{\alpha}{2}[T'_sn - \tau +\Delta t]^2 \right)} $$ where $\tau$ is the travel delay, $f_0$ the start frequency (assumed perfect for simplicity), $\alpha$ the ramp rate, $T'_s=T_s(1+\epsilon)$ the sampling interval of the ADC that potentially deviates from the assumed ideal sampling interval $T_s$, $\Delta t$ the clock jitter and $n=0, 1, \dots, N$ the sample index.

The deramping would be done with an ideal stored chirp in memory (assuming the timing is synchronised) $$ s_{ref}[T_sn]=e^{j2\pi(f_0[T_sn]+\frac{\alpha}{2}[T_sn]^2)} $$

I have written out the outcoming beat signal ($s*_{rx}\cdot s_{ref}$), which gets pretty blown up. Especially when the time delay $\tau$ becomes time dependent due to movement.

EDIT: Here is the deramped signal (without movement) $$ \begin{align} s_{deramp}[n] = &s^*_{rx}\times s_{ref}\\ &e^{j2\pi\left( f_0(T_s-T'_s)n + \frac{\alpha}{2}(T_s-T'_s)^2n^2 \right)} \times\\ &e^{j2\pi\left(f_0(\tau-\Delta t) - \frac{\alpha}{2}(\tau^2+\Delta t^2) + \alpha (\tau-\Delta t)T'_s n + \alpha\tau\Delta t \right)} \end{align} $$ My question is:
Is this model correct or somewhat in the correct direction? Am I misunderstanding something? I am lacking the experience to judge if some of these effects are potentially negligible. If anyone knows resources I could read up about this, a tip would be greatly appreciated!

Hope the question is clear, otherwsie I clarify!

I am currently studying the topic of oscillator phase noise in frequency modulated continuous wave (FMCW) radar. In my specific case, the radar is implemented on an FPGA (AMD RFSoC). Thus, the echo is directly digitized by the ADC after the antenna (and some filter and amp. stages, but no down mixing). Deramping will be done in the digital domain, followed by a digital filter and downsampling to reduce the memory demand.

Now I see a lot of studies on phase noise and radar, but usually they assume the deramping in the analog domain. I have been wondering whether I will get different effects with direct RF-sampling.

For example: The local oscillator used to synthesize the ADC and DAC sampling clocks will have some phase noise and maybe frequency drifts. This would lead to jitter and a sampling frequency drift as I understand. I have not encountered this in literature when the deramped signal is sampled by the ADC.

Now, assuming I receive the echo with an ADC that is driven by a different LO, the phase noise will not cancel out. My idea of an echo model (from point target) looks like this: $$ s_{rx}[T'_s n] = e^{j2\pi\left( f_0[T'_sn - \tau +\Delta t]+ \frac{\alpha}{2}[T'_sn - \tau +\Delta t]^2 \right)} $$ where $\tau$ is the travel delay, $f_0$ the start frequency (assumed perfect for simplicity), $\alpha$ the ramp rate, $T'_s=T_s(1+\epsilon)$ the sampling interval of the ADC that potentially deviates from the assumed ideal sampling interval $T_s$, $\Delta t$ the clock jitter and $n=0, 1, \dots, N$ the sample index.

The deramping would be done with an ideal stored chirp in memory (assuming the timing is synchronised) $$ s_{ref}[T_sn]=e^{j2\pi(f_0[T_sn]+\frac{\alpha}{2}[T_sn]^2)} $$

I have written out the outcoming beat signal ($s*_{rx}\cdot s_{ref}$), which gets pretty blown up. Especially when the time delay $\tau$ becomes time dependent due to movement.

My question is:
Is this model correct or somewhat in the correct direction? Am I misunderstanding something? I am lacking the experience to judge if some of these effects are potentially negligible. If anyone knows resources I could read up about this, a tip would be greatly appreciated!

Hope the question is clear, otherwsie I clarify!

I am currently studying the topic of oscillator phase noise in frequency modulated continuous wave (FMCW) radar. In my specific case, the radar is implemented on an FPGA (AMD RFSoC). Thus, the echo is directly digitized by the ADC after the antenna (and some filter and amp. stages, but no down mixing). Deramping will be done in the digital domain, followed by a digital filter and downsampling to reduce the memory demand.

Now I see a lot of studies on phase noise and radar, but usually they assume the deramping in the analog domain. I have been wondering whether I will get different effects with direct RF-sampling.

For example: The local oscillator used to synthesize the ADC and DAC sampling clocks will have some phase noise and maybe frequency drifts. This would lead to jitter and a sampling frequency drift as I understand. I have not encountered this in literature when the deramped signal is sampled by the ADC.

Now, assuming I receive the echo with an ADC that is driven by a different LO, the phase noise will not cancel out. My idea of an echo model (from point target) looks like this: $$ s_{rx}[T'_s n] = e^{j2\pi\left( f_0[T'_sn - \tau +\Delta t]+ \frac{\alpha}{2}[T'_sn - \tau +\Delta t]^2 \right)} $$ where $\tau$ is the travel delay, $f_0$ the start frequency (assumed perfect for simplicity), $\alpha$ the ramp rate, $T'_s=T_s(1+\epsilon)$ the sampling interval of the ADC that potentially deviates from the assumed ideal sampling interval $T_s$, $\Delta t$ the clock jitter and $n=0, 1, \dots, N$ the sample index.

The deramping would be done with an ideal stored chirp in memory (assuming the timing is synchronised) $$ s_{ref}[T_sn]=e^{j2\pi(f_0[T_sn]+\frac{\alpha}{2}[T_sn]^2)} $$

I have written out the outcoming beat signal ($s*_{rx}\cdot s_{ref}$), which gets pretty blown up. Especially when the time delay $\tau$ becomes time dependent due to movement.

EDIT: Here is the deramped signal (without movement) $$ \begin{align} s_{deramp}[n] = &s^*_{rx}\times s_{ref}\\ &e^{j2\pi\left( f_0(T_s-T'_s)n + \frac{\alpha}{2}(T_s-T'_s)^2n^2 \right)} \times\\ &e^{j2\pi\left(f_0(\tau-\Delta t) - \frac{\alpha}{2}(\tau^2-\Delta t^2) + \alpha (\tau-\Delta t)T'_s n + \alpha\tau\Delta t \right)} \end{align} $$ My question is:
Is this model correct or somewhat in the correct direction? Am I misunderstanding something? I am lacking the experience to judge if some of these effects are potentially negligible. If anyone knows resources I could read up about this, a tip would be greatly appreciated!

Hope the question is clear, otherwsie I clarify!