Skip to main content
Signal Processing
Marty's user avatar
Marty's user avatar
Marty's user avatar
Marty
  • Member for 13 years, 4 months
  • Last seen more than 4 years ago
Profile Activity
Stats
201
reputation
22k
reached
1
answer
0
questions
Communities
View all
About
I'm an IC Digital Design Engineer working in Ireland. I code:
  • RTL in verilog
  • Testbenches in verilog or systemverilog, with a sprinkling of DPI'd C routines for good measure
  • Various scripts in Python, bash and if I have to, Perl

In my spare time, I dabble in PIC and Arduino projects. I've also been known to write tiny GUI programs with Python&[wxPython|pyGTK]

Badges
This user doesn’t have any gold badges yet.
1
silver badge
5
bronze badges
Top tags
10
Score
1
Posts
100
Posts %
Top posts
answer
10
Designing Butterworth filter in Matlab and obtaining filter [a.b] coefficients as integers for online Verilog HDL code generator
Mar 1, 2012
Top network posts
View all network posts
78
How Do I interpret HDD S.M.A.R.T Results?
65
How to declare and use 1D and 2D byte arrays in Verilog?
62
How do I avoid the "S to Skip" message on boot?
57
Any PPAs for Google's Go Language?
36
How to interpret blocking vs non blocking assignments in Verilog?