There is still a loop with an adjustable loop bw: The summing block shown is an indication of the additional integration to create a second order loop, although a proportional path should be included as well in order to maintain stability (PI Loop Filter, here with what is suggesting an accumulator you would only have "I"). I suspect the block diagram is just simplified and the summation shown is intended to be the more detailed proprtional-intergral loop filter structure as shown in your subsequent diagram.  

Even without the summing block this will still be a loop with adjustable loop BW, just not the best choice: in this case it would be a first order loop that will lock to constant error given a constant frequency offset (and be unconditionally stable if not for parasitic delay elements the implementation will invariably have). If the loop gain is large (set by scaling the value at the input to the DDS), then the error can be minimized- but still exists. Adding the additional proportional-integral loop filter before the DDS input will maintain stability and lock to zero error in this frequency offset condition. 

(The DDS, similar to a VCO is directly proportional to frequency- so in units of phase it  forms one integrator in the loop- with the PI loop filter added, we get the second integrator, and with both at DC to form a second order Type 2 Loop).

As I mentioned in the comments, if you do implement this as given, compare results to a fixed scaling (instead of the SNR) and the sign of the signal (instead of tanh) and let us know your results of that versus the optimal implementation shown.