Questions tagged [digital-to-analog]

A digital-to-analog converter (DAC, D/A, D2A, or D-to-A) is a system that converts a digital signal into an analog signal.

Filter by
Sorted by
Tagged with
10 votes
4 answers
5k views

reconstruction filter - How does it actually work?

I'm trying to form my own understanding on the religious war around using 192kHz as a sampling rate for playback (the Internet seems to have a wealth of material on both sides). I'm struggling to ...
user1202136's user avatar
6 votes
3 answers
1k views

What is the gain (advantage) of oversampling and noise shaping in D/A conversion?

It is clear that oversampling and noise shaping in A/D conversion can help in shaping quantization noise. But for D/A conversion, normally there is no quantization and hence I did not understand its ...
DSPinfinity's user avatar
5 votes
2 answers
502 views

How to avoid harmonic distortions in a DAC?

I have a DAC which is assumed to be nonlinear, such that it produces unwanted harmonic distortions at integer multiples of the input frequencies. (EDIT: Any other nonlinear distortions, such as ...
Harry's user avatar
  • 183
5 votes
3 answers
1k views

Digital to analog aliasing or mirror query... DAC can output negative frequency?

Using a clock Fs = 1 MHz. The Digital to Analog (DAC) can make frequencies upto 500 KHz. 500 kHz to 1 MHz is an alias? Or is it called a mirror?? Is aliasing a concept only on the ADC and sampling ...
Natalie Johnson's user avatar
4 votes
4 answers
2k views

From a physics perspective, why does D/A quantization error result in a noise floor?

For the last week or so I have been trying to understand how quantization error results in the noise floor outside of a mathematical perspective and I haven't really had any luck finding a source that ...
user3841's user avatar
4 votes
3 answers
603 views

What causes this type of distortion in a constellation I/Q plot?

I'm transmitting QPSK through a digital pulse shaping filter (RRC, 35% excess BW, 2 samples per symbol, 64 taps) at a rate of 56Msym/sec. Receiving it on standard lab equipment (Vector signal ...
user67081's user avatar
  • 723
4 votes
1 answer
12k views

What is the difference between undersampling and oversampling in analog to digital conversion ?

When converting a signal from analog to digital, we observe undersampling and oversampling. Does oversampling means that the sampling frequency is greater that the signal's frequency and does ...
Nzui Manto's user avatar
3 votes
2 answers
1k views

DAC and ADC architecture in SDRs

What are the DAC and ADC architectures in SDRs for inphase and quadrature phase channels? Do we have separate ADC and DAC for each channel or there is some clever way that they are multiplexed to ...
Dsp guy sam's user avatar
  • 2,610
3 votes
2 answers
5k views

Why analog anti aliasing filter is used before analog to digital converter when there is already a digital filter after ADC?

Normal data acquisition consist of: Analog anti aliasing filter( Sampling frequency : $5\textrm{ kHz}$) ADC - Digital Filter - (Sampling : 200K samples /sec) Digital low pass filters Filters DAC ...
user2121195's user avatar
3 votes
1 answer
3k views

DAC implementation in OFDM

In an OFDM transmitter, after IFFT & CP block, a DAC block is used.Since the output of IFFT is complex, and the input to DAC should be an integer, how can we integrate the two blocks? I ...
Ehsan's user avatar
  • 31
2 votes
2 answers
1k views

How does the RaspberryPi radio hack convert digital GPIO signals to an FM signal?

After having looked at various explanation of how the RaspberryPi FM transmitter hack works, I realize there are some fundamental pieces missing. Most explanations talk about how to construct a ...
not2qubit's user avatar
  • 145
2 votes
3 answers
5k views

What is the difference between (Sample Timing Offset), (Carrier Frequency offset), and (Sampling Frequency Offset)?

Briefly, can anyone explain to me what is the difference between (Sample Timing Offset), (Carrier Frequency offset), and (Sampling Frequency Offset)? and is Sampling Frequency Offset (SFO) like STO ...
Amro Goneim's user avatar
2 votes
2 answers
256 views

What's the model for a DAC followed by a sampler?

I have a situation where a sampled signal is passed through a DAC and re-sampled by a switched capacitor circuit. I can't see a model for this in the literature. The standard model of a DAC is the ...
akellyirl's user avatar
  • 133
2 votes
2 answers
234 views

DSP low pass filter (IIR) no longer works when changed to a new MCU

Having troubles understanding why a DSP low pass filter was that working on the M4 is no longer working on an M7. I recently switched over to a STM32H753ZI from a STM32L432KC. In addition to switching ...
Pllsz's user avatar
  • 139
2 votes
3 answers
432 views

Adding two sine waves results in a low buzz

I'm working on a little audio/embedded systems project, and I'm using synthesis to generate waveforms and feeding them into DAC and speakers. Currently, I am able to produce sine waves of individual ...
TrebledJ's user avatar
  • 121
2 votes
1 answer
75 views

Is the ideal reconstruction process BIBO stable?

It is well known that ideal lowpass filter, i.e. the lowpass filter whose impulse response is $h(t) = \text{sinc}(t)$, is not BIBO-stable because $h(t)$ is not absolutely integrable. However, think ...
avril_14th's user avatar
2 votes
1 answer
1k views

How does the world's simplest sigma-delta DAC work?

I have run into a simple delta-sigma (supposedly, where is the delta part?) DAC implementation utilizing an accumulator and then using the overflow bit as a modulated 1-bit output. From https://www....
jakeh12's user avatar
  • 23
2 votes
1 answer
202 views

Efficient Implementation of Digital Upconversion

I have an application where I have a pulse shaped QAM signal, at 2 samples per symbol. I need to take the I/Q samples and perform quadrature upconversion so that they can be output on a DAC that's ...
user67081's user avatar
  • 723
2 votes
2 answers
268 views

Direct Digital Synthesis - Super Sampling - Unknown Harmonics

I'm using a Xilinx FPGA (Virtex) with 4 DDS cores (each supplied a 250MHz clock) used in parallel to provide a samples to a DAC38J82IAAV from TI, 16 bit DAC running at 1 Gsps. The four cores super ...
Mark73's user avatar
  • 21
2 votes
1 answer
116 views

Why is this ring-buffer jumping?

Central problem (Abstract): A simple implementation of a two-buffer ring-buffer jumps after filling up completely. What am I missing? About: ADC to DAC feedthrough STM32L476RG NUCLEO as MCU Intended ...
jake_asks_short_questions's user avatar
1 vote
3 answers
381 views

Linearizing digital-analog converters

I'm looking at ways to improve the effective resolution of DACs. It seems that element mismatch (i.e. integral non-linearity) is the main contributor to distortion in modern DACs. Apart from ...
Arnfinn's user avatar
  • 1,035
1 vote
2 answers
916 views

Types of interpolation used for reconstruction in DSP?

What are the different types of interpolation used in DSP for reconstruction of analog signal from discrete/digital signal I am able to somehow learn two types of interpolation 1st is "zero order ...
DSP_CS's user avatar
  • 1,910
1 vote
2 answers
114 views

When applying analog and digital effects on an audio signal is it better to start with a clean digital signal or use the analog effects before ADC?

If I am digitally capturing an audio signal from an analog source and I know I will want some analog effects applied, is it better to use them on the analog signal before doing the ADC, or should I ...
hamburgermenu's user avatar
1 vote
2 answers
820 views

Audio processing. Is it possible to directly access the decoded audio data going into the analog input of a computer

When a computer transcodes an audio file from one file format to another, does the computer first decode it into the raw digital stream (exactly what is fed into the DAC for the audio output) , or ...
Engineer999's user avatar
1 vote
1 answer
896 views

DAC and sample and hold effect

I am having some trouble understanding how a digital signal gets converted back to an analog signal. Why is the "sample and hold" effect a problem?
user7277's user avatar
  • 257
1 vote
1 answer
188 views

Attenuation of reconstruction filter for Digital-to-Analogue (DAC) converter

I am using a 12-bit DAC to produce signals between 10 kHz and 400 kHz, produced at a rate of 3.33 MSamples/s (Nyquist frequency of 1.665 MHz). I would like to create a "reconstruction filter"...
Rhodes's user avatar
  • 13
1 vote
1 answer
139 views

Aperture Jitter in Digital to Analog Converters

I have noticed in the literature that there is an internally induced timing jitter inside Analog to digital converters called (aperture jitter). It is caused by the sample-and-hold circuit of the ADC. ...
Amro Goneim's user avatar
1 vote
2 answers
5k views

Bandwidth vs. sampling rate of DAC

What is the difference between the sampling rate and the bandwidth of a DAC? I have found in one paper a DAC speced as 15GHz 3dB bandwidth, and 64GS/s sampling rate, and I haven't been able to relate ...
plavi_zec's user avatar
1 vote
1 answer
146 views

Sampling Precision, Jitter, and PID

I am having difficulty understanding the effect of quantization noise and ADC resolution in a digital PID controller. I am also trying to understand the effects of sampling jitter on a PID controller. ...
FooAnon's user avatar
  • 296
1 vote
2 answers
195 views

Difficulty absorbing Idea of interpolation?

I am trying to develop my understand of interpolation and signal reconstruction and uptill now i have understood that there are 3 commonly studied types of interpolation 1)Zero order hold ...
bnm's user avatar
  • 11
1 vote
1 answer
210 views

DDS generated chirp and antialiasing filter : what is the best suited filter for a chirp?

I am defining the required antialiasing (analog) filter for a chirp generated by a DDS. The chirp is produced in a FPGA (NCO generation) and forwarded to the DAC for the samples generation (with ...
AtoM_84's user avatar
  • 21
1 vote
0 answers
145 views

Analysing DAC Spectra: Transient Noise Analysis

I am working with a new Digital-to-Analog Converter (DAC) design in simulation and I'm trying to analyse the output. The device takes in an ideal 14-bit digital representation of a sine wave and ...
Alex Steven's user avatar
1 vote
0 answers
338 views

First order hold from zero order hold filter

I'm stuck in this question for more than 4 hours. (h is the sampling period) I simplified the block diagram but it just seems impossible to get the FOH transfer function from the reduced block ...
JP1111's user avatar
  • 11
1 vote
0 answers
32 views

What is the pipeline DAC tollerable offset from plot

I have analyzed the circuit in full extent as shown bellow. I know that I showed imagine two-stage back to back and see "which input could handle both". Could you please show how exactly I ...
rocko445's user avatar
  • 171
0 votes
3 answers
431 views

Can a digital signal has 3 three values(1,0 and -1)?

Typically digital signals are seen having only two values,but is it possible that a digital signal has three values(1,0 and -1)?as shown highlighted in attached snapshot,which has been extracted from ...
DSP_CS's user avatar
  • 1,910
0 votes
1 answer
902 views

DDS - Supersampling above the FPGA clock frequency

I'm using a Xilinx Virtex 6 FPGA with 200 MHz clock connected to a 1.6 GSa/s DAC to generate sine waves of up to 800 MHz using 8 parallel Xilinx DDS Compiler IP cores. Initially, I calculate the 32 ...
jake_head1's user avatar
0 votes
1 answer
114 views

explanation of Hybrid systems?

I want to study Detailed explanation of hybrid systems?Which incorporate both continuous and discrete time signals & systems? for example In which a continuous-time input signal is transformed ...
DSP_CS's user avatar
  • 1,910
0 votes
2 answers
64 views

Mapping PAM-17 levels to PAM-5 levels

A $17$-level $\left\{ -4,-3.5,-3,\ldots,0, 0.5, 1,\ldots, 3.5, 4 \right\}$ digital signal coming at $125 \, \textrm{MHz}$ is passed through an FIR filter ($10$ taps) operating at $1250 \, \textrm{MHz}$...
Isha's user avatar
  • 1
0 votes
2 answers
738 views

sigma delta modulator for DAC

Can someone please provide an overview of sigma delta DAC? In particular, I would like to know how does the sigma delta modulator, which is digital, works for DAC. What is difference between sigma ...
user3005720's user avatar
0 votes
1 answer
288 views

sample rate conversion

I have read many of the posts here on the stack regarding sample rate conversion but have yet to find one that does not rely either upon asynchronous or synchronous clocks. It occurs to me that the ...
Ken C's user avatar
  • 1
0 votes
1 answer
169 views

Complete OFDM transmitter chain

I am looking for complete OFDM transmitter chain with all the details i.e. starting from modulation symbols up to up conversion to carrier. What I have found on the web is Modulation Symbols serial ...
user3005720's user avatar
0 votes
2 answers
1k views

How to reconstruct original signal from sampled signal?

My original signal as f1=2; f2=5; fs=100; Ts=1/fs; t=0:Ts:1; xt=cos(2*pi*f1*t)+cos(2*pi*f2*t); figure plot(t,xt) as shown below figure. and my sampled signal ...
agile's user avatar
  • 109
0 votes
1 answer
184 views

Is this an error in Oppenheim and Schafer's Discrete-Time Signal Processing?

In Discrete-Time Signal Processing by Alan V. Oppenheim and Ronald W. Schafer (3rd Ed.), in Figure 4.47 the input of D/A converter is $\hat{y}[n]$ but later in Figure 4.64 the input of D/A converter ...
DSPinfinity's user avatar
0 votes
2 answers
512 views

D/A converter with

I am trying to figure out how to consider digital-to-analog conversion and how to consider oversampling based on a course I am taking online and figuring out the logic behind this. Unfortunately there ...
qxzsilver's user avatar
  • 109
0 votes
1 answer
1k views

Is dithering and noise shaping needed when upsampling an audio signal 8 times (from 44.1kHz to 352.8kHz for example)

The main purpose of upsampling before digital to analog conversion is to move quantization noise far beyond the audible spectrum to be able to filter it out by simple second-order low pass analog ...
e_asphyx's user avatar
  • 137
0 votes
1 answer
975 views

How is a PCM byte converted to a voltage level?

16-bit signed PCM would have possible values of ~-32,000 to ~+32,000. How is this value converted to a voltage level for the speaker? If a DAC outputs 5VAC, the values would be ~+-5v. How is the ...
Kunal Chopra's user avatar
0 votes
1 answer
44 views

DAC/ADC sample rate selection for modem

So I have a very basic on which I couldn't find much details anywhere. I'll start with an example: I have to transmit 100Mbps of BPSK data. Roll-off factor is 0.25. This data will be processed at ...
Rituj's user avatar
  • 3
0 votes
1 answer
43 views

Noise (in dB) added to a signal but within range limits

I have a sine wave signal to which I add noise in terms of dB. This is based on https://stackoverflow.com/questions/14058340/adding-noise-to-a-signal-in-python The signal is sent to a DAC and there ...
Mart's user avatar
  • 195
0 votes
1 answer
50 views

How does PAM-4 encoding of a digital signal relate to theoretical *pulse* amplitude modulation?

Pulse amplitude modulation in general is often explained using plots like this one from wikipedia: There is a sinusoid analog signal (red) to be "imprinted" on a train of pulses. The result ...
JMC's user avatar
  • 101
0 votes
1 answer
100 views

what am i not doing right while using squarewaves?

I have been applying square waves at 40hz and 10 volts via a function generator amplified by a power amplifier by 2 times(2A) on a 6mm steel specimen. My signals captured from the AE sensor are not ...
Wasil Riaz's user avatar