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I found the following diagram of a Farrow Filter online: enter image description here

As far as I understand the purpose of a Farrow filter is to interpolate samples at a fractional ratio. For example: we have an ADC sampling at 83 MS/S and we need to transmit it using a DAC that expects 90 MS/S. The DAC mustn't receive non valid data so me "create" data by interpolating it with a fractional ratio which must be EXACTLY equal to 90/83.

Although absent from the diagram above - for an FPGA/ASIC engineer having 2 unrelated clocks in the system implies using some kind of buffering mechanism (i.e: asynchronous FIFO). This FIFO will be written every cycles of the 83 MS/S side but read at the 90 MS/S side not every cycle to prevent underflow. Because of that, on the 90 MS/S side some samples (when the FIFO isn't read) would be used by the filter twice - which to my intuition feels "strange" because IMO all the 83 MS/S side samples should contribute equally to the generation of the interpolated 90 MS/S side samples.

Seems like there's something fundamentally incorrect in my understanding. What am I missing ?

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I like this diagram a little better (it's equivalent)

enter image description here

Now, while most of the time the Farrow structure is associated with Lagrange interpolation, it need not be Lagrange. It can be any decent polynomial interpolation and I would recommend Hermite, especially if you're going with 3rd-order polynomial interpolation. So then the issue is how to design those FIR filters. I kinda restate the math here but I express it using Horner's rule. That's how you get to the Farrow structure.

Now the issue about the two asynchronous clocks is that your devices is likely to have a system clock that is much faster than either the input sample rate (83 MHz) and output sample rate (90 MHz). Let's say that clock is a couple of GHz. You need to maintain and incrementing counter every time your system clock occurs. You read that counter for every input sample (when that 83 MHz clock occurs) and you read it for output sample (when the 90 MHz clock occurs). You can even record the counter values in a simple FIFO buffer so that you know what it was for the past 16 or 256 samples. From that information you can derive a precise sample-rate conversion factor (which is roughly 90/83) and from that what your step size is (the output pointer increments 83/90 sample steps in your input buffer buffer).

So your output pointer has an integer and fractional portion. The integer portion tells you which adjacent samples you will use and the fractional portion is your $\Delta$ that tells you how you will mix those. In the Farrow structure, you only update your FIR filters when the integer part increments, which it does 83/90 of the time. Most output samples will update the FIR, but not every output sample. But when that integer part does not increment, for sure $\Delta$ is getting incremented. When the integer part does increment, the $\Delta$ wraps around because $0 \le \Delta < 1$ always.

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  • $\begingroup$ Thanks so much for your explanation. I'm working on an FPGA so 2GHz is definitely out of reach. A reasonable system clock for my device will be in the range of 250 MHz. So according to your explanation the structure that you drew will be clocking at 250 MHz ? Do I need to store the incoming samples of the 83 MHz in a FIFO ? $\endgroup$
    – shaiko
    Apr 5 at 20:45
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    $\begingroup$ Okay, there is going to be a lot of jitter between your system clock and your output clock. You not only need to store your incoming samples into a FIFO, but you must store the values of the counter on your system clock into another FIFO and you must store the values of that same counter of your output sampling instances into another FIFO. This is the only way that you will be able to asychronously determine the step size. $\endgroup$ Apr 5 at 20:52
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    $\begingroup$ Do you have the ability to do a fixed-point division with your FPGA? If not, there is a feedback method using multiplication to do it. $\endgroup$ Apr 5 at 21:00
  • $\begingroup$ So in total I would need 3 FIFOs. 1st for the input samples themselves (written to with every new sample), 2nd for a system clock counter snapshot written when receiving a sample. 3rd for a system clock counter written each time a DAC cycle occurs. Is this correct ? Also, when should these FIFOs be read ? $\endgroup$
    – shaiko
    Apr 5 at 21:32
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    $\begingroup$ But if you buffer the output samples, too (so this is a double-buffered sample I/O), then you can reduce the jitter, but even if you do not, the feedback error signal (which is the difference between the output pointer with fractional precision and a fixed delay behind the input pointer), that error signal goes into a servo controller which increases or decreases the the step-size of the advancement of the output pointer each output sample interrupt. I'd write you an answer but I would have to think about this a lot. $\endgroup$ Apr 5 at 23:28

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