I have a Virtex 6 FPGA running at 200MHz with ADC/DACs on it. I have been converting a WiFi signal (2462MHz) down to a more reasonable IF of 25MHz, sampling, running the signal through taps, tweaking them, and mixing back up. This all works fine.
My issue is that since I am mixing down and sampling at a lower rate, I cannot implement RF level multipath by adjusting the delay in the taps for phase changes, instead I had to adjust it at the IF level instead. This works OK, but it means that timing is off (things like TDOA or stuff with TOF measurements could care about that). It seems like the best way around this (and probably the right way) is to implement a fractional delay filter (FDF), but I am not sure the best way to do it.
It seems like I need to come up with the coefficients for the taps, but I cannot seem to glean that out of the whitepapers I've read on FDF. Any ideas?