Performing experiment on a digital control system

I want to perform experiment(s) on a digital control system. I have several questions:

1. In analog control systems, the adder is usually an operational amplifier. However, since here the system will be discrete the adder will be a $$3$$-bit adder, right?

2. A discrete-time discrete-amplitude signal is defined only for time instants that are integer multiplies of the sampling period. Now, the only digital components which could simulate such as a signal are flip flops. However, flip flops introduce a delay of 1 clock cycle they don't work out for me so which digital components should I use?

This is one such control system:

It has a unity negative feedback loop and it the transfer function of the open loop gain is $$\frac{1}{z^{2}}$$ so with the unity negative feedback it becomes $$\frac{1}{z^{2}+1}$$. However, this is not very interesting and it is critically unstable since the poles are exactly on the unit circle.

I want to design out a digital circuit which will be of 2nd order in the $$z$$ domain.

• Yes I will upload it later. Dec 30, 2023 at 12:38
• Digital Signal Processing is about processing analog signals by use of digital means. Dec 30, 2023 at 12:52
• @robertbristow-johnson I know that.I am very curious on what will happen for digital signals.Is it uncharted territory? Dec 30, 2023 at 13:57
• The terms "digital control system" and "digital signals" have well-known meanings that don't match what you're proposing. I'm not sure what are good terms -- "single bit digital" or perhaps "ultra low bit-count digital" may make sense here. If you're just interested in the academic study of control systems with single-bit data paths I suggest you edit your question to expand on what you want to experiment with, and to come up with a name for it that does not clash with the existing names. Don't be surprised at trivial answers -- with 3 bits, there won't be many behaviors. Jan 2 at 18:57

If I am interpreting the OP's diagram correctly, it is a shift register of 3 samples for one bit wide symbol with negative feedback, but a one bit subtraction is the same as a one bit addition, so in the case that is what is actually being done, that would be equivalently positive feedback with unit gain which is unstable (in fact passing in a unit sample will result in a continuous 001001001001001... output).

This appears to be an attempt at implementing an accumulator given the OP mentioned the delays shown are intended to be a 3 bit adder and the intention is to model a digital control loop. In this case all the outputs of the gates would represent the multiple bits in the counter, and a digital adder needs to be included to add the output of the counter to the next input coming from the differencer. The differencer would also need to represent fixed point values over the full operating range of the loop and not just one single bit.

Digital control loops are implemented using an accumulator as the digital "Integrator" as part of the loop filter (or can be entirely the loop filter in first order loops), as depicted in the block diagram below together with its analog counterpart using an op-amp. The control range out of the accumulator would be limited by the accumulator size, so in many cases 3 bits would be insufficient. In this diagram of the accumulator on the left, each path represents a digital word with however many bits are necessary for the digital values to be used. The $$z^{-1}$$ is a register delay of one clock sample, such that after every sample the last output is added to the next input (accumulates). The multiplication with $$\tau$$ is the integration gain and is equivalent to the RC product in the op-amp implementation. $$1/s$$ is the Laplace for a time domain integration, and maps to $$z/(z-1)$$ using the method of impulse invariance (and in this case the Backward Euler substitution of $$s \leftrightarrow 1-z^{-1}$$ as well). Thus the two forms are equivalent with that particular mapping other than the sign inversion with the op-amp implementation.

The implementations for a first order type 1 and second order type 2 digital control loop in simplest form is shown below combining the accumulator with negative feedback and loop gain. Typically the output of the loop filters would be the control input for another digital device whose output is then fed back into the input differencer (but this device may have additional poles and/or zeros which can then further complicate the loop). The second order system as implemented as a "Type 2" (which means two poles at $$z=1$$, as provided by the two accumulators) must include a proportional path to maintain stability, and thus uses a "PI Loop Filter", with Proportional ($$P$$) and Integral ($$I$$) loop gains. These diagrams represent digital paths with high enough precision on each path (multi-bit) to represent all digital values required for the operational range of the loop.

Assuming I didn't make a math error, the transfer functions for the two diagrams above would be:

First order system:

$$H_1(z)= \frac{I\frac{z}{z-1}}{1+\frac{z}{z-1}} = \frac{Iz}{(I+1)-1}$$

Second order system:

$$H_2(z) = \frac{(P+I\frac{z}{z-1})\frac{z}{z-1}}{1+(P+I\frac{z}{z-1})\frac{z}{z-1}} = \frac{(I+1)z^2-Pz}{(I+P+1)z^2-(P+2)z+1}$$

Further, in actual implementation one or both of the accumulators may be implemented as follows which is mathematically identical to the accumulator introduced above followed by an additional delay. If the sampling rate is not significantly higher than the desired loop bandwidth, this additional delay will effect loop performance and stability.

How do I know this? I teach courses on DSP and Python related to wireless comm through dsprelated.com and the IEEE with new courses running soon! The course "DSP for Software Radio goes into the implementation of digital control systems in detail as they are used for carrier and timing recovery in software radio receivers. This course will be running again in late February 2024.

• Hello subtraction is not equal to addition. Jan 1 at 3:43
• Happy New Year! Thinks for reading and commenting. I clarified that I was referring to the 1 bit case (GF(2)), where I believe it is, it is an XOR where 1+1=0 and 1-1=0. Perhaps your diagram represented a higher precision path but that wasn’t clear in the original posting so I needed to add that clarification. Jan 1 at 14:17
• Happy New Year!Its fine thanks for taking the time to answer my question. Jan 1 at 14:31