# Fixed point number scheme IIR filter with ADC

I am a student working with digital circuits. I just started a term project with someone else working on an ADC. I need to design a IIR filter in verilog.

If the output of an ADC represents 1V by setting all output bits to '1' and 0V by all bits to '0', and I wanted to use a fixed point scheme for the filter coefficients, what do I expect from the output signals? I am a little confused about:

1. Is the ADC output a fixed-point format, or it shouldn't be considered as any format?
2. What does the output of my filter represent? If some of the coefficients are negative, what does a negative output mean?
3. If the coefficients are represented in Q6.10 format for example, does the output need to be shifted?

Sorry if the questions seem quite naive, I have very limited exposure with DSP. Thanks.

Fixed point processing especially for IIR filters is quite complicated.

The main challenges are

1. Make sure you don't overflow or clip for all filter coefficients and signal types.
2. Make sure you end up with sufficient signal to noise ratio for your application
3. Avoid spurious artifacts like limit cycles.

Some general rules that make this easier:

2. Use Direct Form I (safest and easiest) or Transposed Form II structures. Do NOT use Transposed Form I or Direct Form II.
3. Use a double width accumulator for each section if you have it
4. Throw a few extra bits at it if you can. Optimizing the bit width down to the last bit is an enormous amount of work.

Is the ADC output a fixed-point format, or it shouldn't be considered as any format?

It's fixed point format. Most common is 2's complement.

What does the output of my filter represent? If some of the coefficients are negative, what does a negative output mean?

Your output is the convolution of the input signal with the impulse response of the filter. And yes, both coefficient and the output can be negative unless you design your filter specifically to avoid that.

If the coefficients are represented in Q6.10 format for example, does the output need to be shifted?

Generally you try to shift your output and ANY intermediate result and state variable so that it can be as large as possible without clipping.

As far as I know now, most ADC and DAC chips communicate to their CPU or DSP chip over a serial protocol with 3 wires (word/frame clock, bit clock, data) and the data is represented as a twos-complement integer. But you should consult the spec sheet of the ADC/DAC chip and get all of the particulars. Representations such as Q6.10 or such really are in the mind of the programmer. The fixed-point twos-complement bits are exactly the same whether you consider it Q1.15 or Q2.14 or Q6.10 . That scaling factor is up to the programmer.

Now the Q scaling of the coefficients, that's a little different. That gets defined by the way you extract the 16-bit result out of the 32-bit words that result when you multiply two 16-bit numbers together. You really do have to consider that in advance.

If you're doing an IIR, numerical issues can get a little funky and you do need to worry about them. Maybe this answer will give you some insight in how to think about doing fixed-point IIR.