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Say I have a 10-bit SAR ADC with a $5 \ \text{V}$ reference. I calculate its resolution to be

$$\Delta V_\text{lsb} = \frac{5 \ \text{V}}{2^{10}} = 4.88 \ \text{mV} \approx 5 \ \text{mV}. $$

So for a $5 \ \text{mV}$ increase (or decrease) the LSB of my ADC will toggle.

Assuming that the dynamic range of the ADC is $6 \ \text{dB}/\text{bit}$ one gets the total dynamic range to be

$$\text{DR} = \frac{V_\text{full-scale}}{V_\text{quant-noise}} = 60 \ \text{dB}.$$ Incidentally, performing this next calculation yields

$$\frac{5 \ \text{V}}{10^{\frac{60\ \text{dB}}{20\ \text{dB}}}} = 5 \ \text{mV}.$$

To me, the resolution and dynamic range look like they characterize the same thing: For a $5 \ \text{mV}$ increase (or decrease) the LSB of my ADC will toggle. So I'm struggling to see the difference between them.

Also, what would happen if my 10-bit ADC (for some reason) had $\text{DR} = 40 \: \text{dB}$ instead of $60 \ \text{dB}$? The ADC resolution would be unchanged (it still has 1023 discrete voltage levels), but when would the LSB toggle?

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3 Answers 3

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ADC resolution is the level of one quantization step in the units of magnitude desired (such as volts to refer to the input, or counts to refer to the digital output levels). The resolution is the value of 1 lsb for a given ADC, as the step size that will be created from each lsb count just as the OP has computed: ~5 mV as 1 count in the OP's example, and that is correct for an ADC that provides 10 actual bits with a range of 0 to 5V.

ADC dynamic range is typically considered to be the ratio between a full scale sine wave and the noise floor of the device, specified as the total power over the unique digital frequency range (either $-f_s/2$ to $+f_s/2$ when we refer to two-sided spectrums, or DC to $+f_s/2$ when we refer to one-sided spectrums). This ratio is referred to as SINAD (Signal to Noise and Distortion Ratio). It is when dynamic range is defined this way specifically (ratio of power in a full scale sine to the total power in the noise of the ADC), then we get the relationship:

$$SINAD = 6.02 \text{ dB/bit} + 1.76 \text{ dB}$$

Definitions can vary so it is important to refer to the documentation for a specific ADC manufacturer when reading their datasheets. It is best to use the term SINAD directly as we can arrive at many other concepts of what dynamic range can mean, just as the OP has done- or other applications where we modify the dynamic range through subsequent filtering, or have different concepts in what a minimum discernable signal is, etc. Basically "dynamic range" on its own leaves a lot of room for different interpretations if there isn't a specific and clear definition with it. The OP is referring to Dynamic Range as the ratio of a full scale DC signal to one quantization level. This is a valid definition if clearly articulated, but that will not be a signal to noise ratio nor will it be equal to 6.02 dB/bit + 1.76 dB. In that case, just as the OP has determined, the ratio in dB would simply be 6.02 dB/bit.

Another term often associated with ADC dynamic range is ENOB (Effective number of bits). If the ADC was perfect, then the noise due to it's operation would be from quantization alone. Actual ADC's have additional noise sources (such as shot noise and spurious signals due to non-linearities) that increase the overall noise floor of the device, resulting in a reduced SINAD. The ENOB is a figure of merit that provides us the number of bits for a perfect ADC that would result in the same noise floor and it is derived from the dynamic range relating the power in a full scale sine wave to the total power in the noise (in contrast to the OP's dynamic range definition).

Thus, the relationship between SINAD and ENOB is given by rearranging the first equation given above as:

$$ENOB = \frac{SINAD-1.76}{6.02}$$

For the derivation of the above formula, and more details on the relationship between SINAD (SNR) and number of bits, and further introducing the effects of oversampling, please see DSP.SE post 40261.

As an example of the possible confusion with dynamic range, below is a simulation with the OP's case of a 10 bit ADC with an input range of 0 to 5V, that has a dynamic range of 40 dB (for clarity, this example 10 bit ADC has a SINAD that is 40 dB). For this, I created showing what the output waveform could look like for this specific ADC if we were to input a DC level equivalent to 110 counts ($5 *110/2^{10}= .53711V$) for a duration of 20,000 samples, followed by a DC level of 111 counts ($5 * 111/2^{10} = .54199V$) counts for 20,000 samples. Note that the ADC output changes (in steps given by its resolution) over a range of roughly 100 to 120 counts. Importantly the lower plot shows what the result would be if we were to average multiple readings such that in this case, the ADC can discern the 1 count step! This shows that the ADC does still in fact "react" to the change of the input given we derived this result from the ADC output samples alone, and in fact we could use such averaging to discern even smaller fractions of a count. What we are seeing is that when we put in a higher value, all the samples that are output on average will be higher than when we put in a lower value. This is oversampling which can be used to increase the dynamic range of an ADC further, and thereby increasing ENOB.

step

Below is a zoom in of the upper plot above, where we can discern the actual counts as the ADC output provides, representing the ADC resolution:

ADC Resolution

The 10 bit ADC, if it were perfect without the additional noise degradations (ENOB = 10 bits), under conditions of a full scale sine wave would result in the waveforms shown below, showing the analog input in units of counts, the quantized input, and as the difference between the two, the quantization error.

ADC ENOB=10 bits

I computed in this experimental simulation for the ENOB =10 bits case, the standard deviation of the full-scale input sine wave as $\sigma_s = 362.04$ counts, and the standard deviation of the quantization noise as $\sigma_n = 0.29$ counts (note for the latter that the predicted quantization noise as detailed in the referenced post above is $1/\sqrt{12} = 0.2886$).

Thus the measured SINAD in dB is:

$$SINAD = 20log_{10}(\sigma_s/\sigma_n) \text{ dB}= 20log_{10}(362.04/0.29) \text{ dB}=61.90 \text{ dB}$$

And the predicted SINAD for a 10 bit converter is:

$$SINAD = 6.02 \text{ dB/bit} + 1.76 \text{ dB} = 61.96 \text{ dB}$$

With the additional noise degradations, the sine wave as sampled above is still sampled into levels as given by 10 bits, but the additional noise is added to the sine wave effectively prior to being sampled, such that we still have the output changing in counts of the lsb, but with a much wider standard deviation as an error from the ideal sine wave with no noise added. So we still have 10 bits or 1024 unique levels coming out of the ADC, it's just that those levels include additional noise. This is shown in the graphic below where we see a much larger spread for quantization noise (as the error between what the output count tells us and the actual input signal):

SINAD 40 dB

Where here the standard deviation of the noise is now $\sigma_n = 3.56$ counts, and the measured SINAD is given as:

$$SINAD = 20log_{10}(\sigma_s/\sigma_n) \text{ dB}= 20log_{10}(362.04/3.56) \text{ dB}=40.15\text{ dB}$$

With this, we could back out the number of bits for an equivalent perfect ADC that would provide the same noise level as an rms quantity relative to a full scale sine wave:

$$ENOB = \frac{SINAD-1.76}{6.02} = \frac{40.15-1.76}{6.02}= 6.4 \text{ bits}$$

In summary the above shows the behavior of the LSB, and how it would toggle in all cases. But the representation of the resulting digital sample as either signal or noise (and ultimately a combination of the two) depends on the SINAD performance of the ADC.

The tutorial MT-003 by Walt Kester at Analog Devices is helpful in understanding all the noise sources that contribute to SINAD, including the variation in how this definition is used by different vendors.


The OP has continued questions in the comments:

"But we know that the ADC can't possibly measure signals below 4.88 mV if it has to have quantization levels of equally spaced in 1024 counts in the range from 0-5V. This is where my confusion lies"

This was for the case of a perfect 10 bit ADC with a range of 5V, such that one quantization level is $5/2^{10} = 4.88$ mV. And it is true that the ratio of full scale as 5V to 1 count as 4.88 mV or $1/2^{10}$ is $-20Log_{10}(2^{10}) = 60.2$ dB. Yet the formula "6.01 dB/bit + 1.76 dB" results in 61.86 dB and is associated with the "Effective Number of Bits" for 10 bits. So the OP is confused why we would call that the Effective Number of Bits, since a count level in dB that is 61.86 dB below a full scale DC signal of 5V would only be $5 \times 10^{-61.86/20}= 4.03$ mV.

This is because the dynamic range predicted by the formula 6.02 dB/bit + 1.76 is NOT the ratio of a full scale DC signal to a peak to peak count level ($q$). It is well defined as the ratio of the power in a full scale sinusoid (which to start is 3 dB lower than the power in the full scale DC signal!) to the ratio of the power in the quantization noise. The quantization noise is a uniform distribution $\pm q/2$, and for such a distribution the variance (which is the power) is $q/12$.

As far as not measuring signals below 4.88 mV- for a perfect ADC measuring a signal with no other added noise this is true, the ADC won't register any change just as the OP imagines if the signal never crosses a quantization threshold level. But if there are other noise sources present that exceed a threshold level, the ADC will be able to react to and measure much lower levels (as I demonstrated in the first graphic above). But that is really an aside, the main point is we are predicting a noise power level (as we would want for any SNR measurement), and that prediction applies under test with a full scale sine wave. The full scale sine wave will create a noise when sampled that has a standard deviation of $q/\sqrt{12}$. So if we measure actual noise levels higher than that, at the ADC output, then we can roll that into an equivalent perfect ADC with less bits, based on the standard deviation of the noise actually measured. What is convenient about this prediction, is that the power in the quantization noise as an absolute level, holds up quite well for other signals as long as the ADC doesn't go into clipping; so with that we can predict the SNR due to the ADC noise for other arbitrary waveforms. In the OP's case of a 6.4 bit ENOB and 5V peak signal, the standard deviation of the full scale sine wave is $V_p/\sqrt{2} = 1.77$ V rms. The standard deviation of the quantization noise is 40 dB lower or $1.77/10^{40/20} = 17.7$ mV rms. If we were to put in a lower level arbitrary waveform that had a standard deviation of 250 mV (for example), the standard deviation of the quantization noise would still be approximately 17.7 mV rms. This is the primary convenience of that formula for purpose of predicting SNR, and with that a measure of the dynamic range we can operate in based on our actual minimum SNR requirements.

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  • $\begingroup$ This answer has some valuable information, but it is not what I'm looking for. Specifically, I am looking for why the general formula for ENOB tells me that in the scenario described in my question and in my answer we have $\text{ENOB} = \frac{40 \ \text{dB} - 1.76 \ \text{dB}}{6.02 \ \text{dB}/\text{bit}} = 6.35 \ \text{bits} $ when in reality we have $\text{ENOB} = \frac{40 \ \text{dB}}{6.02 \ \text{dB}/\text{bit}} = 6.644 \ \text{bits} \ $. $\endgroup$
    – Carl
    Oct 13, 2023 at 18:45
  • $\begingroup$ Thanks. I think my linked answer can help you with that. Were you aware that the 6 dB / bit + 1.76 dB comes from full scale for a sine wave not a DC signal? A full scale sine wave has an RMS level that is 3 dB lower and the noise itself is the total rms noise due to quantization which is the step size $q$ divided by $\sqrt{12}$. Is that what was confusing you? If you go through those two relationships rigorously (as my other answer does) you get the equation 6 dB/bit + 1.76 dB as predicting the total power in the quantization noise below the power of a full scale sine wave. $\endgroup$ Oct 13, 2023 at 18:48
  • $\begingroup$ What confuses me is that if the ADC only recognizes voltages in steps of $50 \ \text{mV}$, then there are 100 quantization steps from $0$ to $5 \ \text{V}$. So ENOB should be $6.644 \ \text{bits}$ because $2^{6.644} = 100$ which makes sense. However, in the theoretical calculation for ENOB we have that little -1.76 dB term that messes the calculation up, and instead gives that ENOB is $6.35 \ \text{bits}$ which doesn't make sense to me since $2^{6.35} = 81$. But we have just figured out that there are 100 quantization levels, not 81. So the theoretical formula must be wrong in this case. $\endgroup$
    – Carl
    Oct 13, 2023 at 18:53
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    $\begingroup$ Yes let me try to make that a little clearer in the opening paragraph- if I have time I'll throw in some illustrations. (I have to step out but will add that later, I get your confusion!) $\endgroup$ Oct 13, 2023 at 18:56
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    $\begingroup$ @Carl See my update, I hope it gets to the point of confusion. $\endgroup$ Oct 15, 2023 at 4:17
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A 10-bit ADC with a $5 \ \text{V}$ reference has the relative amplitude resolution

$$\Delta V_\text{lsb} = \frac{5 \ \text{V}}{2^{10}} = 4.88 \ \text{mV}. $$

For an input voltage of $4.88 \ \text{mV}$ the ideal ADC would display: 0000 0000 01 (binary)

For an input voltage of $9.76 \ \text{mV}$ the ideal ADC would display: 0000 0000 10 (binary)

And so on...

The dynamic range tells us the minimum input voltage the ADC will recognize, with respect to the full-scale voltage. If this ADC thus has a dynamic range of $40 \ \text{dB}$ then the minimum voltage the ADC can recognize is

$$V_\text{min} = \frac{5 \ \text{V}}{40 \ \text{dB}} = 50 \ \text{mV} $$

So even though the bits of the ADC permits a visible change in the input voltage of $4.88 \ \text{mV}$ the insufficient dynamic range limits the ADC, such that a change of $50 \ \text{mV}$ is required for the ADC to react. This has these consequences:

For an input voltage of $4.88 \ \text{mV}$ the ideal ADC would display: 0000 0000 00 (binary)

For an input voltage of $9.76 \ \text{mV}$ the ideal ADC would display: 0000 0000 00 (binary)

...

For an input voltage of $48.80 \ \text{mV}$ the ADC displays: 0000 0000 00 (binary)

For an input voltage of $53.76 \ \text{mV}$ the ADC displays: 0000 0010 11 (binary)

From $0$ to $53.76 \ \text{mV}$ the ADC skips $10$ quantization levels before finally reacting which means that not all possible bit combinations of the ADC bits will be utilized. From $0 \ \text{V}$ to $ 5 \ \text{V}$ there are $100$ quantization levels, with a step size of $50 \ \text{mV}$.

The effective number of bits is not equal to the theoretical number (10) but is in actuality

$$\text{ENOB} = \frac{40 \ \text{dB}}{6.02 \ \text{dB}/\text{bit}} = 6.644 \ \text{bits} \ $$

which makes sense since $\text{quantization levels} = 2^{6.644} = 100$.

The general formula says that

$$\text{ENOB} = \frac{40 \ \text{dB} - 1.76 \ \text{dB}}{6.02 \ \text{dB}/\text{bit}} = 6.35 \ \text{bits} $$

but that can't be true, since $2^{6.35} \approx 81$.

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The difference between the resolution and dynamic range used in ADC characterization

As with many other special terms of signal processing and electronic engineering, these words are typical cases of polysemy. To understand their meaning, you have to be careful of context. When charaterizing A/D converters, 'resolution' is used interchangeably with 'bit depth'. As for 'dynamic range (DR)', it is typically defined as 'the ratio between the largest and smallest values that the ADC can reliably measure' (or should we say 'difference', because it is measured in decibels?). In this aspect, 'ADC resolution' and 'ADC DR' do characterize the same thing, but remember that 'dynamic range' can measure the performance not only of an ADC device per se, but of the cascade 'variable gain amplifier (VGA)' + 'ADC', the use of VGA significantly improving the total DR. The noise shaping technique is another technique that improves the system DR without resorting to bit depth increase.

Summing up, 'ADC resolution' is about the quantization step and is a fixed parameter, while, changing the reference voltage of a conventional ADC or use VGA to fit the dynamic range of the input signal, we can have the better measurement precision without increasing the ADC resolution.

To add to a possible confusion, the exact meaning of ADC DR can slightly vary among the fields where ADCs are used, as telecommunications, digital audio, SDR, measuring instrumentation, etc. In my writing, I tend to avoid the use of an 'ADC dynamic range' construct, setting apart the use of DR for characterisation of signal power, voltage, current parameters that can be input to/output from as diverse units as sensors, signal conditioning and signal processing circuits, audio amplifiers, transceivers etc.

But the most confusing about the 'ADC dynamic range' wording used to name the quantity $2^N$, where $N$ is an ADC bit depth, is that this quantity is not dynamic at all. As well as 'resolution', when used to characterize the ADC device only, it is a static parameter.

Of course, this precaution should be taken only when using the generic term 'dynamic range'. The specific DR terms, as spurious-free dynamic range (SFDR) and intermod-free dynamic range, are well defined, have unambiguous meaning, and can be used without reservation.


Your bonus question what would happen if my 10-bit ADC (for some reason) had DR=40dB instead of 60 dB? is answered by Walt Kester in the Analog Devices' tutorial Taking the Mystery out of the Infamous Formula, "SNR = 6.02N + 1.76dB," and Why You Should Care, section CORRELATION BETWEEN QUANTIZATION NOISE AND INPUT SIGNAL YIELDS MISLEADING RESULTS -- if your some reason is the result of jitter noise, ADC glitch, unsuitable signal conditioning or the like. Of course, you can invent some reason that is not covered in Walt Kestler's article. The article may probably help you explain the "paradox" of inconsistent ENOB calculations in your self-answer, although I didn't quite get what you mean.

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