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If this is not the right StackExchange group, please advice.

I seem to have the same problem as 1 (2019, on the miniDSP forum, unanswered) with the NotWired NW-AUD-ICS52000 boards. I have had no other boards with which to test the TDK InvenSense ICS-52000 mics.

The NotWired NW-AUD-ICS52000 board is at 3, and the TDK InvenSense ICS-52000 chip is at 4.

I do hear noise, that's all, all the time. But it differs somewhat in quality. But it's kind of whiteish noise I'd guess.

For me it's a long story, I have fiddled with my own driver in xC, running on XMOS boards, and scoped everything during the development, and found out that it must be the board (99% confident). Using the same SW driver for the PCM5100A on 3, the headset mics do work. I have also tested the headset driver with a sine of 640 Hz and it sure beeps.

I have scope pictures that I can publish. Since I discovered someone else with the same problem my confidence that it's the board rose from 50% to 99%! This is a hobby project so there is nothing I can't disclose.

Even for the 99% I do have some questions that I might make another thread for. Like, is the InvenSense ICS-52000 data sheet 100% correct? Or, is there no contradictions in it?

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1 Answer 1

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It turned out that the NotWired NW-AUD-ICS52000 boards did not work (with my SW drivers, I tested several). They only produced noise.

When I received the alternative single-mic boards EV_ICS-52000-FX (here) my SW drivers, which had been unmodified since the last tests, worked right out of the box, so to say.

Another interesting thing is that I was able to pull in two audio channels at 32 kHz (16 kHz each, SCK 1.024 MHz) as well as a single channel at 16 kHz (SCK 512 kHz). The ICS-52000 data sheet (here) would say "The frequency of SCK will depend on the number of microphones in the system. The SCK frequency should be n × 32 × fS, where n is a power of two (2, 4, 8, or 16) equal to or greater than the number of ICS-52000s on the bus. Table 8 shows the recommended SCK frequency for a chain of ICS-52000 microphones." Table 8 also lists 1 channel, which I guess the description also should have done, since $2^{0} = 1$.

All of this also worked with somewhat asymmetrical SCK (but within SCK duty cycle specs) but with the sum giving 100% accurate 32 or 16 kHz. Therefore I did not have to use an external PLL for this (XMOS X2 core) design.

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