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I have an FPGA that is limited in clock frequency, but receives data from a higher sample rate ADC by receiving N samples per clock cycle (all N samples are from a single ADC channel). So the FPGA has to operate on N samples per clock cycle instead of 1. Now say I want to implement a generic FIR filter to operate upon this stream. Are they any neat tricks or smart ways to implement this, or is this simply an exercise of taking the filter equation and unfolding it to perform the equivalent of N iterations per clock cycles?

I want to clarify that this is not asking about multirate filters or changing sample rates, I should still get N filtered samples out per clock cycle.

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  • $\begingroup$ Check your FPGA vendor's IP catalog and see if they support FIR cores with sample rates greater than clock rates, presumably they would do it fairly efficiently. I know that Xilinx/AMD supports this, don't know about Altera/Intel. $\endgroup$
    – Jason C
    May 7, 2023 at 12:36

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Transposing the FIR filter lends itself well to parallel processing as each input can be applied to all multipliers at the same time. Below shows a typical FIR filter in Direct Form where the input is sequenced through a shift register and then applied to each multiplier with the output of the multipliers summed. The filter is transposed by changing summing nodes to branch nodes, branch nodes to summing nodes, and changing direction of all signal flows as shown in the lower diagram. This structure if used directly with a register after each summation will extend the maximum clock frequency, as delays can otherwise accumulate in the larger adder trees of the Direct Form structure causing timing issues at the higher rates. Below shows how it can be used in parallel form with all operations done at a lower frequency.

transposed filter form

The operations are described below where each row represents the input sampling rate, $d_0, d_1, d_2, \ldots$ repesents the input data , and $w_0, w_1, w_2, w_3$ represent filter coefficients. Here for each four input sample events given as $\phi_1, \phi_2, \phi_3, \phi_4$, the output samples are computed $y_0, y_1, y_2, y_3$ then after the next four input sample events, the next four output samples are computed, all in parallel.

parallel operation

Using the graphic from the paper linked at the bottom of this post, in parallel form the transposed FIR filter (assuming 4 taps as I had done above) becomes:

parallel form

Further references detailing this:

https://vhdlwhiz.com/part-2-finite-impulse-response-fir-filters/

https://www.atlantis-press.com/article/23421.pdf

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