How to compensate phase delay introduced by the digital integrator?

Question

Let's say I have a digital integrator with transfer function in following form

$$ \frac{Y(z)}{U(z)} = \frac{T}{2}\cdot\frac{z + 1}{z - 1} $$

I have been looking for a mechanism how to compensate the phase delay introduced by the integrator. My first idea how to do that was to use a digital derivator with a filtering pole. To verify my idea I have exploited the analog counterparts

• Integrator

$$G_i = \frac{1}{s}$$

• Derivator

$$G_d = s\cdot T_d,$$ $T_d = 1.0\,\mathrm{s}$

• Filtering pole

$$G_f = \frac{1}{T_f\cdot s + 1},$$ $T_f = 0.01\cdot T_d\,\mathrm{s}$

The associated bode plots for the transfer functions above

Based on the bode plots above I have judged that the compensation via $\frac{s\cdot T_d}{T_f\cdot s + 1}$ (after discretization) should be functional. But I am not sure whether the step with transformation of the problem completely into the $s$-domain is correct. Please can you tell me whether the approach I have used for the design of the compensation is correct? If not please can you recommend me the correct approach?

Answer 1

More generally “lead” and “lag” networks are used for phase compensation. In simplest form they have one pole and one zero where for a lead network $|z|<|p|$, meaning the zero is placed further away from the origin than the pole in the left half plane (inside the unit circle for discrete time), and for a lag network $|z|>|p|$. So if we want to increase phase margin, a lead network is employed. Both can be used as a lead-lag network where typically the lag compensator pole zero pair are closer to the origin than the lead compensator’s pole zero pair which provides the desired phase lead at higher frequencies to ensure stability.

Another similar example compensation for the phase introduced by an integrator (accumulator for discrete time) is to use a Proportional Integral solution (PI Loop Filter in control loops) by adding a direct proportional path around the integration. Here a zero is introduced which has a phase that increases by +90 degrees asymptotically with frequency. For control loops in general stability can be determined (for the cases when there aren’t any unstable open loop poles) by reviewing the Bode Plot of the Open Loop Gain (break the loop and measure the transfer function)-- the system is stable if the gain has gone below 0 dB by the time the phase reaches -180°. The integrator makes the gain in the Bode Plot goes down by -6 dB/octave (and the phase approaches -90 degrees). Typically there is another integration in the system (such as a VCO) motivating the need for the zero), resulting in the gain dropping by -12 dB/octave and the phase approaches 180 degrees (oh no!). The zero brings the gain back to a -6 dB/octave slope (so slows the gain decrease which isn't great) but importantly pulls the phase back up away from approaching 180 degrees (yay!). Finally, not yet mentioned, but a higher frequency pole is also typically introduced once we are past 0 dB gain to filter higher frequency noise. The zero and the higher frequency pole can be viewed as a lead compensator for the additional integrator added.

The frequency response of the "PI Filter" is given as:

$$H(s) = K\frac{s-z_1}{s}$$

And for a discrete system as:

$$H(z) = K\frac{z-z_1}{z-1}$$

Below are example analog and digital implementations:

Continuous time PI loop filter construction with an op—amp (for voltage input, voltage output solutions):

Discrete time PI loop filter construction:

And other forms depending on how the integration operation is mapped from analog to digital. The figure above uses the Method of Impulse Invariance (also same as Matched-Z in this case). Below is the same using the Bilinear Transform: