The log2 computation is really a consideration for the size of the (extended precision) accumulator for a fixed point FIR filter design:
The sum of the absolute value of the coefficients is the predicted maximum bit growth in the accumulator, but to note importantly after accumulation the output can be truncated (or rounded if DC offset error is a concern) back to a much smaller bit width. Further and importantly we must also consider the precision of the coefficients and any rounding or truncation that might be done at each multiplier output.
As a guideline, the bit width for the output should typically be $log_{10}(f_s/(2f_c))$ bigger than the bit width of the input where $f_c$ is the bandwidth of the low pass filter (for example with a quarter-band low pass filter, the final output should be 1 bit larger than the input to support the expected 6 dB decrease in noise floor). This assumes our input bit width is limiting our noise floor and cannot be decreased without decreasing our SNR.
Further, as a guideline the coefficients themselves should be at least 2 bits wider than the datapath (you will get 5 to 6 dB of stop band rejection for every bit used in the coefficients), but this can be easily verified by reviewing the frequency response with the fixed point coefficient values. With a 19 bit input and 21 bit coefficients, each multiplier if 2s complement signed would have a $19+21-1=39$ bit output without additional truncation error. Not all of these output bits are needed and can be truncated somewhat; without doing a detailed model I would suggest carrying 4 extra bits or 25 bits at the multiplier output into the accumulator and thus use a $25+18=43$ bit accumulator which is then truncated back after accumulation as I first advised.
This assumes all 19 bits of input precision are actually required, and follows the approach I suggested since quantization (rounding or truncation) noise at the multiplier outputs grow by $N$ in power to the FIR filter output (as detailed in the graphic below), while the output quantization when truncated or rounded there is only added once. That said, the truncation or rounding at the multiplier outputs can be done if kept to sufficiently low levels and depends on FIR filter length. (And to see with that hopefully how it would be really bad to truncate or round the multiplier outputs back to the 19 bit datapath precision inputs!). My approach is to use the guidelines I provided and then confirm SNR a performance via fixed point simulation.
