0
$\begingroup$

I want to implement an IIR filter. The filter is going to implement by cascading second order sections. Below there are 3 pictures that implement this filter using:

  1. Denominator - Numerator using Tapped Delay Line Structure 2:
  2. Numerator -Denominator using Time Delay and Accumulate Structure 3:
  3. Denominator - Nominator using Time Delay and Accumulate Structure

(1)

enter image description here

(2)

enter image description here

(3)

enter image description here

a,b: coefficients

I want to examine the efficiency of the structure due to dynamic range and ease of implementation. I also want to use only one multiplier in the architecture. I think it is easier to implement the structure with less delayers but what is the dynamic range and how i can find it??

$\endgroup$
6
$\begingroup$

Peter's correct. at least if fixed-point arithmetic is used. the DF2 has poles before zeros. that means the signal is getting boosted by the poles before the zeros (which are often sitting very close to the poles) beat the gain back down to reasonable levels. so if the signal overflows, saturates, and distorts due to this gain, the attenuation offered by the zeros does not reverse that distortion error. it's too late.

now the DF1 implements the zeros before the poles, and if you did not have an accumulator that has a double word width, then the DF1 suffers a sorta opposite flaw. instead of potentially overflowing (and saturating) due to gain from the poles which is what the DF2 does, the DF1 will have attenuation first (due to the zeros) followed by the compensating gain from the poles. if the accumulator is no wider than the signal word going in, there is roundoff error due to quantizing the attenuated signal. then when the poles act on the attenuated and quantized signal, that quantization error is boosted by the poles.

BUT if your DSP (or whatever processor you use) has an accumulator that is twice the width of the two multiplicands, there is no roundoff error for the poles to boost. so the DF1 avoids the overflow problems of the DF2, but if and only if there is a double-wide accumulator, does not suffer from boosting the roundoff error.

$\endgroup$
  • 2
    $\begingroup$ Great to see you here, rbj! :-) $\endgroup$ – Peter K. Apr 13 '13 at 19:09
  • 3
    $\begingroup$ hadn't even known of this site before you told us about it on comp.dsp . it looks like it might have a higher S/N than comp.dsp since it appears to be more restrictive and/or moderated. thanx Peter. $\endgroup$ – robert bristow-johnson Apr 13 '13 at 21:44
3
$\begingroup$

Please see this write-up by Julius O. Smith III on the Direct Form II filter structure. One issue with "canonical with respect to delay" filter structures is that they can be subject to overflow.

I'll need to go through it completely, but I believe structures (1) and (2) in your question will be subject to this possible overflow.

Are you implementing this in fixed point arithmetic? Do you have a known input range?

I was a little confused by your diagrams: what I believe you are using for delay elements would normally be gain-only (amplifiers). Delay elements are usually drawn differently.

$\endgroup$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.