Sigma Delta with counter instead of filter

Question

in most applications the 1-bit output datastream of a sigma-delta ADC is converted via a filter. What's the advantage over counting the ones/zeroes and averaging over the results? For a simplified design i want to avoid something like an FPGA and use a µC (32-bit ARM) instead. In contrast to filter calculations, counting pulses requires next to no load on the µC. My basic idea is:

1. count the amount of 1's over 2^N clock pulses (e.g. 16 bit = 65536 pulses)
2. inspect the result to account for ADC behaviour (e.g. values that indigcate out of range)
3. calculate arithmetic mean of the last X results (e.g. 16)

What are the disadvantages over the classic approach?

Answer 1

counting the ones/zeroes and averaging over the results?

That's a filter, already. A moving-average filter! All low-pass filter are essentially summers with varying weights.

A moving average is convolution with a rectangular window; which implies a sinc spectrum. This might or might not be what you desire as an ADC designer. Generally, Sigma-Delta ADCs are popular due to their inherent noise shaping stemming directly from their architecture – and with the way you integrate has an influence on that.

So, by choosing to weigh the last N samples with individual coefficients before summing them up you get a chance to adjust your quantization noise shaping.

Answer 2

Adding to Marcus' good answer: a single counter (moving average filter as he correctly pointed out) is not appropriate as the complete filtering solution for any practical Sigma Delta converter used. This is because such a converter would always be of higher order (typically 3rd order or higher) and with that the noise shaping would increase versus frequency much faster than a moving average filter will attenuate. The moving average filter has a Sinc shaped frequency response, and with that the peaks are decreasing at a first order rate or -20 dB/decade. (And even a 2nd order Sigma Delta converter will have noise increasing +40 dB/decade!). The filtering solution used must exceed the order of the sigma delta converter at least from the desired bandwidth out to half the higher sampling rate of the converter to provide adequate noise reduction and the expected increase in precision. (This can be accomplished with multiple moving average filters in cascade, as done easily with higher order decimating CIC filter implementations).