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I have a classifier that is trained on a dataset sampled at 100Hz. I am using this classifier on a MCU (the teensy 4.0 dev board) for inference and not training. However, the ADC chip I am using samples at 250, 500, 1k, 2k, .... The simplest thing I can think of is set the ADC to sample at 500 Hz, and take the average of every 5 samples collected (to avoid aliasing). However, I would like to sample at 250Hz and resample to 100Hz. are there any C/C++ libraries that do this efficiently? or if not, if there is an algorithm I could be directed to, I can take it on from there.

EDIT: the ADC used is the 24-bit ADS129x chip from TI. in terms of signal processing, there is an anti-aliasing filter on the board with corner frequency of 1.1KHz, and digital IIR BP filtering between 5-20Hz.

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    $\begingroup$ I know this may sound like a wrong solution from a theoretical signal processing view how it should be done, but since you have not told how the signal is preprocessed in analog domain before the ADC, and what ADC it is and how it operates, so you should fill that in. But from the ADC point of view, if ADC type and signal conditioning is propely taken into account, it may simply take samples and it may be equal to take samples at 500 Hz and take every fifth sample than just sampling at 100 Hz. Please fill in the signal, ADC and analog conditioning details before ADC. $\endgroup$
    – Justme
    Jan 1 at 18:30
  • $\begingroup$ @Justme thanks, added the info $\endgroup$
    – NeuroEng
    Jan 3 at 17:12

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Assuming that filtering doesn't mess up the training, your 500Hz and decimate by 5 idea should work. It'll probably take less processing power than sampling at 250Hz and using a polyphase filter.

But -- for non-integer sampling rate changes, you want to use polyphase filtering. There's material out there on how to do it: the bare bones is that you'll have a pair of FIR filters, one that you run on an ADC sample, and one that you run 2.5 ADC samples (10ms) later. If you design the filter taps correctly, you'll be at some good compromise between added delay and fidelity between the two outputs.

An alternative that may well work is to always average the last $N$ samples (I'd start with three, because -- intuition). Then run your classification algorithm at 2, 3, 2, 3, etc. samples. As long as your classification is not heavily dependent on smooth representation of trends, you'll be OK.

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  • $\begingroup$ thanks, as I am trying to minimize the computational cost, I think averaging 5 samples is the way to go. this does not directly relate to the question, however, since the buffers I save the data in to feed into the classifier are massive, this would added extra burden on the memory. but that's a different thing to deal with. $\endgroup$
    – NeuroEng
    Jan 3 at 17:14
  • $\begingroup$ You said that the cutoff frequency of the filter before the ADC is 1.1 KHz. Are you sure you won't have aliases with a 500 Hz ADC? Why not sampling at 2KHz? $\endgroup$
    – user51024
    Jan 3 at 21:56
  • $\begingroup$ @gotchi85 I did wonder this, and asked about it as well, the response I got was that since the ADC is oversampling and has decimation filters, cheap stable ceramic caps would be more than enough before feeding in the signal into the ADC. $\endgroup$
    – NeuroEng
    Jan 4 at 16:28
  • $\begingroup$ All signals which are above the ADC frequency are going to alias and be captured by the ADC. So they have to be rejected by a filter before entering the ADC. You should check the reponse of this filter with your need to be sure all is under control $\endgroup$
    – user51024
    Jan 4 at 17:37

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