# Distributed Arithmetic FIR Vs basic FIR digital implementation

I make a comparison between the basic FIR filter Vs Distributed Arithmetic FIR

## Second: DA FIR

Then, I implemented Distributed Arithmetic FIR Filters by 2 methods:

## 1st: Serial

If the input sample is M bits, so the FIR needs M clock cycles to generate the output

When implemented, it produced optimized area and power results from synthesis than basic FIR,

But when I uses x6 clock frequency, to make the I/O rate equal, the power and area becomes higher

## 2nd: Parallel

It use parallelism and doesn't use accumulator, so it needs just one clock cycle to generate an output

The power and area numbers are higher than the basic FIR

So, what is the advantage of DA filter than basic FIR filter ?

So, what is the advantage of DA filter than basic FIR filter ?

Pretty much all the cases where I can think of this actually having an advantage involve a signal whose sampling rate is lower than your FPGA's achievable clock rate. It's a slam-dunk if the signal's sample rate times the FIR filter length is less than the FPGA clock rate. In this case then you can use your "serial" architecture and some sequencing logic to iterate the "serial" filter once per sample using multiple FPGA clock ticks.

If your signal sample rate is similar to the FPGA clock rate then you pretty much have to use a parallel architecture (and if it's larger then you have to get fancier yet).

Depending on the length of the filter and the disparity between clock and sample rate, the serial architecture will sometimes use less area.

Notes:

• The end point of this thinking is a DSP chip or a general-purpose processor.
• All problems in engineering, and certainly in any sort of signal processing, involve finding a not-necessarily-intuitive solution that works. So you need to be in the habit of looking at a new solution that seems strange to you and working through how it may be better -- or worse -- than the ones you're used to.
• Thanks for answering, but if the sampling rate is lower than the FPGA clock, I can reduce the clock and using the basic FIR filter design so it will save me power consumption Commented Dec 17, 2022 at 15:57
• And how will that be reflected in the cost and availability of the FPGA? If you use $N \cdot k$ LUTs and clock at a rate $F$, then how is your power consumption different when you use $N$ LUTs and clock at a rate $F / k$? Commented Dec 17, 2022 at 16:02
• If I use N⋅k LUTs the power consumption and area will be bigger as also I will need extra adders to add the outputs of these LUTs (Parallel architecture) while N LUTs with clock rate F/K this is the serial one, but what I mean that when I use F rate with the normal FIR architecture, it saves me power and area, I can't relate effect of FPGA to choose the best choice Commented Dec 17, 2022 at 16:38
• "Pretty much all the cases I can think of involve a signal whose sampling rate is lower than your FPGA's achievable clock rate" You are lucky, in my case I usually face the opposite situation, which requires strong parallelization.
– Vito
Commented Dec 18, 2022 at 6:50
• @Vito: Thanks -- you made me realize that my wording on when a serial architecture would be useful was unclear. Commented Dec 18, 2022 at 17:59