I am using MATLAB to simulate the DUC and DDC process of USRP N210. I have encountered some doubts. As I understand the DUC, the sampling rate of the incoming signal is set by the user (e.g. 12.5M). USRP first buffers the signal through a FIFO and then reads the signal to the interpolation filters (DUC) with the same frequency as the set sampling rate. Please let me know if my description is not clear.
- The DAC of N210 (AD9777) should be driven by the output sample rate of DUC. I found that according to the user manual AD9777 has an input sample rate of 160M and an output of 400M. So the sample rate of the DUC output of the N210 is 160MSps? How does USRP interpolate signals beyond 100M at a clock frequency of 100M?
- the input signal is interpolated and filtered according to (HBF1, HBF2, CIC) in DUC, how is the output sample rate implemented when it exceeds the clock rate(100M)? (For example, the last level of CIC filtering output)
- I got from the Internet that the clock frequency of the digital filter is not related to the output sample rate when a real-time operation is not required. So is the sampling rate of the digital filter (DUC) implemented on N210 related to the clock frequency?