# Questions about the output sampling rate of the DUC(interpolation filter) of the USRP N210

I am using MATLAB to simulate the DUC and DDC process of USRP N210. I have encountered some doubts. As I understand the DUC, the sampling rate of the incoming signal is set by the user (e.g. 12.5M). USRP first buffers the signal through a FIFO and then reads the signal to the interpolation filters (DUC) with the same frequency as the set sampling rate. Please let me know if my description is not clear.

1. The DAC of N210 (AD9777) should be driven by the output sample rate of DUC. I found that according to the user manual AD9777 has an input sample rate of 160M and an output of 400M. So the sample rate of the DUC output of the N210 is 160MSps? How does USRP interpolate signals beyond 100M at a clock frequency of 100M?
2. the input signal is interpolated and filtered according to (HBF1, HBF2, CIC) in DUC, how is the output sample rate implemented when it exceeds the clock rate(100M)? (For example, the last level of CIC filtering output)
3. I got from the Internet that the clock frequency of the digital filter is not related to the output sample rate when a real-time operation is not required. So is the sampling rate of the digital filter (DUC) implemented on N210 related to the clock frequency?

Best Regards,

Ze

I found that according to the user manual AD9777 has an input sample rate of 160M and an output of 400M. So the sample rate of the DUC output of the N210 is 160MSps? How does USRP interpolate signals beyond 100M at a clock frequency of 100M?

It's up to some frequency. The input interface works well with lower rates.

So, the clock rate here is really 100 MHz.



Addresses how computations are done internally in a filter and is irrelevant to the problem of sampling rates. (The question there is "how fast are arithmethic/logic operations done, relative to the sampling rate", and the answer is, well, that depends, on how you build your filter internally. It's very irrelevant to your simulation, though, because for that what counts happens in sample values, and rates, and delays in full samples, not in how fast e.g. a single internal multiplier is clocked.

• So what frequency does the final output sampling rate of the DUC module in the FPGA depend on? As far as I know, after the sampling rate fs set by the user, the DUC performs interpolation filtering on the input signal (fs). The interpolation scale is fOut/fs. I began to think that fOut=400M because the website of Ettus stated that the sampling rate of the N210's DAC is 400MSps. But I checked the schematic of N210 and found that the input frequency in the user manual of the DAC chip is 160M. Dec 8, 2022 at 11:15
• It is not 160 MHz. I addressed that in my answer. Dec 8, 2022 at 11:28
• Sorry, I don't quite understand. How should I determine the output sample rate of the DUC in FPGA? Ettus website labeled N210 has a 400M sample rate DAC, which means the DUC output sample rate of N210 is 100MSps, and then input to DAC, the DAC performs 4x interpolation on the input signal. The final parameter of 400MSps was obtained. Is that right? Dec 8, 2022 at 12:21
• It's 100 MHz. I wrote that. Dec 8, 2022 at 13:37
• Thank you. So the DUC output sampling rate of N210 equals the clock frequency. The DAC of N210 is labeled 400MSps, does the DAC perform interpolation? Dec 12, 2022 at 12:12