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I have an analog value coded as an analog PDM stream, which has a toggling frequency $f_{PDM} \approx$ 100 kHz when the value is at midscale.

I am demodulating this value into a 32 bit result with a simple shift-subtract IIR lowpass filter. Precisely, I am taking the difference between input value $x[n]$ (either 1 or 0) and the filter output value $y[n-1]$. Then I right shift the difference 16 bits and add this to the output:

$$y[n] = y[n-1]+(x[n] - y[n-1]) >>16$$

My first intuition was: Simply sample much faster than the PDM can toggle, and I began with 10 MHz. However, what seemed to happen is that the long consectuive runs of input 1s and 0s appeared to "eat up" the filter dynamic range. Indeed, the result seemed more robust when the PDM was sampled only at 5 MHz.

However, I cannot get too low, because otherwise I would miss pulses when the PDM produces short pulses when the analog value is close to one extreme of its range.

With 5 MHz sampling rate I get about 14 noise-free bits of resolution in the resulting 32 bit number. If I am not mistaken, I should be able to get over 15 noise-free bits (optimally) because I use the 16 lower bits for feeding measurements into the average.

So instead of trial and error I wondered if there is a generic answer to such kind of problem ?

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2 Answers 2

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uniform-time ADC-based sampling of PDM

no matter how fast you could sample, your ADC needs an analog anti-aliasing filter. That's the key here:

Your AA filtering inherently "sums up" the past pulses. You don't sample the PDM signal itself, you sample the output of that filter, which will be higher, the more pulses occurred lately. So, pick an anti-aliasing filter that's appropriate for the bandwidth of the analog signal, and filter your PDM with that: the output will be a relatively faithful reconstruction of the original analog signal. Sample that with the ADC, at a sample rate defined by the bandwidth of the analog signal, so, significantly below 100 kHz, not at 10 MHz (wowzers!).

(I'll invite you to model the actual output of this stochastically: Usually, you'll end up saying "OK, this is the sum of the same impulse response sampled at different times, where the times are independently random, so this is a sum of $N$ i.i.d. variables of known variance, and we know that this has $N$ times that variance, and thus, we get, on expectation, something proportional to the PDM-modulated analog signal, added to noise, which is the more Gaussian, the higher $N$ is (thanks to the central limit theorem)", but there's a couple important assumptions you'd be making on the way. Especially, this quantization noise is not white!)

Frequency counter sampling

The above method is of course highly inefficient. What you usually do (and microcontrollers have timer/counter units designed exactly for this kind of thing, and it's trivial to implement in digital logic) is simply have a counter that counts the pulses (e.g. by counting rising edges). You then read that counter periodically. You can then either reset it to 0 when you read, or just generally subtract the last count value, and get a sequence of numbers representing how many pulses occurred since last counter readout.

Now, the number of pulses in a time period is proportional to the analog amplitude prior to PDM, so you then low-pass filter that to get a discrete-time representation of the analog input signal. The quantization noise is differently shaped in spectrum compared to the method above.

Tying it together: $\Delta\Sigma$, friends!

analog signal -> PDM -> Pulse Counting -> count sampling -> digital filtering

order of
magni-
tude of
bandw.: kHz'es   MHz        MHz              kHz               kHz

That's practically a Delta-Sigma converter, which is probably the most prolific ADC architecture in the world! Every midrange microcontroller has one, your phone's microphones are sampled with such, so is its ambient brightness sensor, and so are probably the oscillations in the tiny MEMS accelerometer observed. So, I think, reading up how a Delta-Sigma converter works, how its noise is shaped, and why you'd want that: Your

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  • $\begingroup$ I know that this is esentially a low cost DS ADC. I even made a post about it in your 555 topic over at EE.SE ;) My IIR filter has a very low corner frequency of ~1 Hz, Marcus. The whole point of sampling the PDM directly with the FPGA and using a digital LP filter, is that I don't need an ADC, only a PDM modulator and some FPGA logic. It also works beautifully. I was just wondering - generally - how much oversampling is good for this kind of acquisition, because the finite filter dynamic range prevents that ever more oversampling is ever more beneficial. $\endgroup$
    – tobalt
    Jun 24 at 13:01
  • $\begingroup$ Ah I think I get it now. Instead of just using a digital LP filter to demodulate the signal with fixed sampling frequency, I should instead just count the pulses. I will think about that. Thanks! $\endgroup$
    – tobalt
    Jun 24 at 13:23
  • $\begingroup$ @tobalt exactly! In your FPGA, have a counter clocked by the PDM signal (every FPGA designer will tell you that's a terrible thing to do, but if it synthesizes, it synthesizes. Some FPGAs also have counter units that can be used for this.); make that counter have a latch that is clocked from your logic, and make that latch "copy" the counter value. But yeah, if your FPGA is fast enough, anyway, just regularly sampling a digital input works just as well, just count the low->high transitions :) $\endgroup$ Jun 24 at 13:31
  • $\begingroup$ Ah I realize the source of my confusion now. It appears my modulation isn't actual PDM. But rather it is PWM with variable frequency (lower towards the extremes of the analog value, so the narrow pulses get longer). Demodulation is merely the average value hence my IIR LP attempt. Not sure if this modulation has a unique name..Ill accept this and make a new question with the correct modulation info. $\endgroup$
    – tobalt
    Jun 24 at 14:29
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    $\begingroup$ instead of counting the rising edges, just count the high instants sampling uniformly in time $\endgroup$ Jun 24 at 14:50
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I'm not familiar with PDM, but the rule of sampling in general is to have a sample rate at least twice faster as the maximum frequency of the signal want to digitalize Nyquist-Shannon Theorem to have zero ambiguity.

You could oversample with high frequency first and decimate at the right time when the signal rises or fall. And maybe it is inconsistent because your samples "slide" on your PDM signal because the sample rate is not sync on the bitrate, wich is accentuated with high sample rate.
I'm not very experimented so maybe the last advice is complete garbage, it was more of a thought or an intuition.

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    $\begingroup$ ah, re: Nyquist: in general, you'd be right, but PDM is just pulse-density modulation. The information is in "in a window of length x, how many pulses are there"; as such, you're not trying to reproduce the PDM signal in the discrete-time domain, but the original signal – you literally do not care about the PDM signal aliasing. $\endgroup$ Jun 24 at 11:35
  • $\begingroup$ Hi, ok I see, like some kind of pwm ? Anyway thanks for taking the time to explain, have a nice day $\endgroup$ Jun 27 at 9:19

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