I have a Xilinx FPGA running at 200MHz with an ADC and DAC on board. I am taking a 2462MHz sine wave (pretending it is 802.11b chan 11), mixing it down to 40MHz putting it through my FPGA, mixing it back up and looking at it on a Spectrum Analyzer.
I have 4 taps (255 clock delays deep) to play with in my FPGA and am currently only using 2 of them. I worked out the phase delay on each tap index by saying that the phase for a particular index (i) is phase=i*(2*pi)(2.462e9/200e6). So index 1 has a phase of 0.13(2*pi) and index 250 has a phase of pi.
Armed with that, I put my signal through with no delay on the first tap, and then delayed the signal on my second tap by 250 clocks (so it should be 180 degrees out of phase). Yet the signal doesn't disappear on the specAn. I haven't found a tap that does make the signal cancel out, so that was where I was curious what I was doing wrong.
I was hoping there was something simple I am missing, as opposed to finding out it can't be done without implementing some sort of fractional delay filters (or something to that effect).