# simulating multipath via tap delays in FPGA

I have a Xilinx FPGA running at 200MHz with an ADC and DAC on board. I am taking a 2462MHz sine wave (pretending it is 802.11b chan 11), mixing it down to 40MHz putting it through my FPGA, mixing it back up and looking at it on a Spectrum Analyzer.

I have 4 taps (255 clock delays deep) to play with in my FPGA and am currently only using 2 of them. I worked out the phase delay on each tap index by saying that the phase for a particular index (i) is phase=i*(2*pi)(2.462e9/200e6). So index 1 has a phase of 0.13(2*pi) and index 250 has a phase of pi.

Armed with that, I put my signal through with no delay on the first tap, and then delayed the signal on my second tap by 250 clocks (so it should be 180 degrees out of phase). Yet the signal doesn't disappear on the specAn. I haven't found a tap that does make the signal cancel out, so that was where I was curious what I was doing wrong.

I was hoping there was something simple I am missing, as opposed to finding out it can't be done without implementing some sort of fractional delay filters (or something to that effect).

• So if I understand correctly, you are trying to coherently jam the analog 2462MHz sine wave by perfectly destructively interfering with it? – Jim Clay Mar 13 '13 at 13:03
• Correct, basically I am just trying to prove to myself that I understood how the phase was working (by jamming myself). – toozie21 Mar 13 '13 at 13:11

Perfect destructive interference is possible in theory, but very difficult to do in practice without feedback to dynamically adjust. The reason for this is that there are three things you have to get just right to eliminate the tone: frequency, time (or equivalently, phase), and amplitude. If you get any of those wrong there will still be a tone (or rather, two tones) left over.

Frequency No matter what you do at the baseband level (i.e. in the FPGA), the frequency will not match if your upmixing does not exactly match your downmixing.

Time/Phase This is a lot more complicated than you realize. First, your phase-per-tap calculation requires that the sinusoid be exactly 2.462GHz and that your FPGA frequency be exactly 200MHz. Neither one is. You can never get an exact frequency, there is always some error and jitter. If you take the derivative of the phase-per-tap with respect to the sinusoid frequency (2.462GHz), you will find that the phase per tap is very sensitive to sinusoid frequency errors.

You have also not taken into consideration the time delays through your ADC, DAC, and connectors, passive analog components, etc. They all matter too. Long story short, I would not try to figure out the correct delay, I would empirically see how the jammer's phase relates to the original sinusoid and adjust from there. Yes, you will almost certainly have to use fractional delays.

Amplitude Even if you get the frequency and phase right you will only be changing the tone's magnitude unless you match its amplitude.

I hope that see that you have taken on a very difficult task. Since you are only trying to test simulated delays, I would find an easier way to do that. I would look at using chirp signals, and then vary the delays to move the responding chirp in time.

• Thank you so much for the detailed response Jim. Since the two taps are being summed back up within the FPGA, I guess that I was ignoring the delays on the ADC/DAC and connector since it is a constant on the one signal and would factor out. I am also using the same LO (via a splitter with two 20dB pads on the outputs to try to dampen leakage) for both mixers, so in theory those freqs should be spot on. The delays within the FPGA could be different for the two different paths, and that might change between builds. Would a mixed-down freq not a multiple of clock freq be advantageous? – toozie21 Mar 13 '13 at 13:52
• I'm not clear on whether you are doing the destructive interference inside of the FPGA or whether you are doing it at the analog level at 2462MHz. – Jim Clay Mar 13 '13 at 14:49
• Sorry, in my head it is so clear, not so much typed out. The interference is being done on the FPGA. I sum the current value of the taps and output it to the DAC to look at the system. If I want to delay the signal on the second tap by 250 clock cycles (which I thought was 180 deg out of phase), It gets pushed into the current index plus 250. – toozie21 Mar 13 '13 at 15:02
• Good, that's a much easier problem. The "frequency" and "amplitude" sections of my answer are mostly non-issues then. You just need to get the timing/phase right. You say that the sinusoid is mixed down to 40 MHz. That means that the phase per tap is $2*\pi*\frac{40E6}{200E6}=0.4*\pi$. You should thus get 180 degrees (i.e $\pi$) at 2.5 taps. No integer number of taps will get you 180 degrees. If you change the sinusoid to 50 MHz then the phase per tap is $0.5*\pi$ and 180 degrees is 2 taps. – Jim Clay Mar 13 '13 at 16:25
• Ah, OK, that makes sense. I was slightly off on my understanding of the calc, but I was doing something like this originally. It makes me wonder if I am screwing something else up mentally:If I wanted to delay the second tap by 400ns say (b/c ray tracing software says it is the delay time), do I need to do a conversion since I am mixing down to 50MHz, or is that purely a time thing, so I could just delay by 80 clock cycles (which is what I was doing since running FPGA at 200MHz). Your response above is making me think that it is mixed down freq dependent. Thanks and I Will try above today! – toozie21 Mar 14 '13 at 10:28