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I'm trying to design an FIR filter with gain = 1 on DSP processor that does not support floating representation. I'm using MATLAB to design the filter and then transport the taps into my code. The problem is that MATLAB returns floating point coefficients that are not compatible with my requirements. of course I tried multiplying the coefficients by $2^{15}$ but that would result in a massive gain to the filter and may saturate my signal and cause an overflow. I would appreciate some help and insights if I'm missing something. Thanks!

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  • $\begingroup$ Are you confident you understand fixed-point processing? $\endgroup$
    – Jazzmaniac
    Commented Feb 4, 2022 at 10:26
  • $\begingroup$ @Jazzmaniac Ahm yes I think so. $\endgroup$
    – Euler
    Commented Feb 4, 2022 at 10:29
  • $\begingroup$ As far as I know TI has at least two, and as many as four, different flavors of fixed-point DSP cores. Please edit your question to say which processor you're using. $\endgroup$
    – TimWescott
    Commented Feb 5, 2022 at 17:16

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If I understand correctly, you are doing a 16 bit fixed-point FIR filter with coefficients equal to 1.

If all other coefficients are smaller than 1, the solution will be very simple. Since multiplying a number by 1 is equal to itself, just omit the step of multiplying by 1 and add it directly to the accumulator. For example, say you have an FIR filter [b0, b1, b2], The filtering process is given by the following difference equation

y[n] = x[n] * b0 + x[n-1] * b1 + x[n-2] * b2;

For fixed-point version, assuming that b0 = 1, b1 and b2 are smaller than 1, the Q15 coefficients would be B1 = round(b1 * 2^15), B2 = round(b2 * 2^15), we don't need to calculate B0 in Q15 format.

acc = (int)x[n] << 15;   // accumulator is in Q31
acc += (int)x[n-1] * B1;
acc += (int)x[n-2] * B2;
y[n] = (short)(acc >> 15);

If any of the other coefficients are greater than 1, instead of multiplying by $2^{15}$, you should use a smaller power of two. In this way you sacrifice the quantize resolution but avoid numeric overflow. After the filtering process, a post shift on the output is required. For example, say the FIR filter is [b0, b1, b2] = [1.0, 1.5, 0.8], then you have Q14 coefficients [B0, B1, B2] = round([b0, b1, b2] * 2^14), and the filtering process is given by

acc = (int)x[n] * B0;
acc += (int)x[n-1] * B1;
acc += (int)x[n-2] * B2;
y[n] = (short)(acc >> 14); // post shift by 14 bits since coefficients are Q14
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  • $\begingroup$ Thanks for the answer. I have two follow-up questions, what do you mean by add directly to the accumulator? Are you familiar with the Q15 TI representation? $\endgroup$
    – Euler
    Commented Feb 4, 2022 at 10:41
  • $\begingroup$ @Euler see my edits $\endgroup$
    – ZR Han
    Commented Feb 4, 2022 at 11:00

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