I have a system I'm working on that inputs an 18 bit ADC output into an FIR filter on a Xilinx FPGA. I'm a little concerned I may be representing the numbers wrong. My ADC outputs a signed 18-bit number.
- I treat the ADC output as a fixed point decimal with one integer (the sign bit, MSb) and 17 fractional bits.
- I represent my FIR filter coefficients as signed decimals, ranging between -1 and 1. I am unsure what the 'right' precision is to use.
- I do not want any gain in my FIR filter, just attenuation in the stop band.
I see two ways to do this -- treat everything as an integer or treat everything as a decimal, each signed with the MSb the sign bit. Provided the output isn't a huge bit width, I have good flexibility to accomodate different fractional / integer widths on the output.
Which is the correct approach? I generate my filter coefficients with Python, what format should I bring them into (integer v decimal)?
Is there a good algorithm approach for choosing the number of bits I used to represent the coefficients?