It's hard to come up with a general answer to such a question, because CPU architectures, especially those specialized for signal-processing applications, are all different. In most cases, you shouldn't have to worry about execution-unit synchronization on processors that support parallel execution of some combinations of instructions. In order to achieve such parallelism, there are often some criteria that must be met, such as:
Inter-instruction dependencies (or data hazards), where the output of one instruction is the input to a subsequent one, can cause pipeline stalls if the previous instruction's latency is too large.
Often, you'll need to ensure that your input data is stored in a memory that is fast enough to support parallel execution. As an example, on TI C5000 architectures, there are two flavors of internal RAM: DARAM (double-access RAM) and SARAM (single-access RAM). In order to fully utilize the dual MAC units on the processor, your input data must be in DARAM, or the memory interface won't be fast enough to feed the execution units.
If you meet these processor-specific constraints, then typically, the processor's pipeline logic is smart enough to know this and automatically forward instructions to the appropriate execution units, so that the process is transparent to you. It might be more involved than this on more complicated architectures: I seem to recall that some TI C6000 DSPs, for instance, had a pipeline with less protection, so by ordering instructions incorrectly, you could get undesired operation (whether that was reduced performance or incorrect answers, I don't remember).