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I understand that a digital signal processor consist of multiple MAD (muliply add units), which execute in parallel to implement a difference equation, like this one:

$$ y[n]=10y[n-1] + 45y[n-2] + 45y[n-4]+ 67x[n]$$

and this one;

$$ y[n]=10x[n-1] + 45x[n-2] + 45x[n-4]+ 67x[n]$$

My question is do I need to be careful about synchronization as we do when programming a multicore CPU/GPU and FPGA? If not why?

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It's hard to come up with a general answer to such a question, because CPU architectures, especially those specialized for signal-processing applications, are all different. In most cases, you shouldn't have to worry about execution-unit synchronization on processors that support parallel execution of some combinations of instructions. In order to achieve such parallelism, there are often some criteria that must be met, such as:

  • Inter-instruction dependencies (or data hazards), where the output of one instruction is the input to a subsequent one, can cause pipeline stalls if the previous instruction's latency is too large.

  • Often, you'll need to ensure that your input data is stored in a memory that is fast enough to support parallel execution. As an example, on TI C5000 architectures, there are two flavors of internal RAM: DARAM (double-access RAM) and SARAM (single-access RAM). In order to fully utilize the dual MAC units on the processor, your input data must be in DARAM, or the memory interface won't be fast enough to feed the execution units.

If you meet these processor-specific constraints, then typically, the processor's pipeline logic is smart enough to know this and automatically forward instructions to the appropriate execution units, so that the process is transparent to you. It might be more involved than this on more complicated architectures: I seem to recall that some TI C6000 DSPs, for instance, had a pipeline with less protection, so by ordering instructions incorrectly, you could get undesired operation (whether that was reduced performance or incorrect answers, I don't remember).

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That's heavily dependent on the processor. The difference equations that you list as an example, is an IIR filter. Here the result for the current sample time depends on the result from the previous sample time. That really doesn't parallelize well and so multiple multiply add units aren't very useful. This is different for a FIR filter where every filter coefficient can run on an individual multiplier.

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  • $\begingroup$ so if I consider FIR, what is the guarantee that all MADs running on individual MAD units will be finished at exactly same time (if we cant guarantee this then lots of problems will come as we face in parallel computing on GPU) $\endgroup$ – gpuguy Mar 8 '13 at 6:44
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    $\begingroup$ That depends heavily on the individual processor. You need to read the hardware reference manual and/or the application manual to find out. If the processor is designed with FIR filtering in mind, you'll typically find reference code or a library from the vendor that will do this correctly. $\endgroup$ – Hilmar Mar 8 '13 at 12:01

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