# I am working on chirp signal generation using DDS in verilog . To generate the chirp signal do I need to change the limit of the 8 bit counter?

I want to generate linear frequency modulated (LFM) waveform or a chirp signal using DDS in verilog. I am not using DDS IP Core. I have created DDS module using 8-bit rate counter, a 12-bit address counter, and an 8-bit by 4096-line sine RAM to produce sinusoidal signal. I am stuck with how to incorporate the chirp rate and go further.

I tried to implement this block diagram:

To generate the chirp signal do I need to change the limit of the 8 bit counter? I got some reference from Can someone help me with chirp signal generation using direct digital synthesizer(DDS) in verilog? , but now I am stuck.

Use a single counter of even higher precision (as is typically done) and then just select the 12 most significant bits out of that one counter to be your address counter. The counter output represents a scaled phase versus time, and selecting the most significant bits is referred to as "phase truncation". The Look Up Table is effectively doing the trigonometric operation of returning the sine of the phase. The phase therefore ranges from 0 to $$2 \pi$$ as the address counter goes from $$0$$ to $$N$$ for $$N-1$$ address locations. The amount of precision to use in the first counter will set the frequency resolution that each step will represent (as detailed in the post referenced in the question).
Below shows a different but typical NCO implementation. The block with the $$z^{-1}$$ represents a unit sample delay, such that the output is the previous output plus the current input (an accumulator or counter). By changing the input word (step size) we change the rate that the counter increases and eventually overflows. It is very important that it wrap on an overflow. Every overflow ends up being one cycle through the LUT or one cycle of the sine wave output: