I try to implementation radix-2 DIT FFT algorithm in FPGA. However, I don't understand that how to set to bit growth for multiply and add process of twiddle factor and input data.
For instance, my input data is 13 bit signed number with a fraction of 0 bit (sfix13_0) and my twiddle factor is 16 bit signed number fraction is 15 bit (sfix16_15). So first step is multiply these two numbers. After that, I add first sample of input and output of multiply operation . I get 32 bit signed number with a fraction of 15 bit. There is the problem is that if I do 10 stages for FFT algorithm, my output has really big bit depth.
How to set bit depth after multiply and add operations for every stage? What kind of operation should be done without spoiling the FFT result and how can we explain it theoretically?
For example, I simulate bit growth in MATLAB for 16 point FFT and 4 stages. However, I reach 128 bit signed number with 60 bit fraction. I think if I apply this approach for 10 stages, the output would be achieved very very high bit depths.
I add MATLAB output:
This image has input and output data. In the left hand side in picture shows inputs, in the right hand side in the picture show outputs, middle in the picture shows multiply and add operations (called butterfly).
How can I handle this bit growth especially integer part while doing 1024 point FFT?