I have an application where I have a pulse shaped QAM signal, at 2 samples per symbol. I need to take the I/Q samples and perform quadrature upconversion so that they can be output on a DAC that's operating at a (real) sample rate of 8 times the baseband IQ rate. The IF frequency is at 1/4 of the DAC's sample rate.
The usual method I would use to do this in an FPGA would basically be the below structure:
where in this case I would have the resamplers just be 8x interpolating FIRs, and the NCO would be replaced with a sequence of [+1,0,-1,0,..] due to the IF being at Fs/4 simplification.
In total this takes the resources required to implement the two FIR filters and a few adders (For doing the negation of the -1 term and the final subtraction operation). Other than using more efficient methods for the FIR filters (like polyphase or CICs) - is there an additional simplification to be made here or is this about it?
I am interested because someone recently proposed to me a method which used 4x upsampling FIRs, followed by [+1,-1,+1,-1] sequence (Fs/2 mixer), followed by a serializer (that basically took the final I/Q samples and simply serialized them before sending them to the D/A - which I guess acted to provide the final 2x).
This approach didn't make sense to me how it would work, specifically the serialization step (I would've thought you'd need to replace the serializer with a 2x upsampling and a subtractor). Although from a frequency domain perspective it does look like its doing the same downconversion as the other method, it seemed to impart some significant distortion onto the constellation when I ran actual qam data through it.