# what is the effect of variation of duty cycle of sampling frequency on a reconstructed signal

I have been asked to study an experiment which says "what is the effect of variation of duty cycle of sampling frequency on a reconstructed signal"

I am not an electronics/electrical engineer I am CS guy.This experiment probably is a part of Analog to Digital Converion techniques, by now I have been able to understand Nyquist theorem and reconstruction is based on this.But for above experiment I am not clear with what to do or study so far what ever I have googled has not given me fruitful results let me know if some one has an answer to above problem.Following is the link which I have studied and could follow http://mhakhan.tripod.com/07sampling.pdf a bit for the above question,what is exactly the thing which I should search?

• What do you mean by "duty cycle of sampling frequency?" Do you mean non-uniform sampling (i.e. the time duration between each sample is not constant)? In the vast majority of cases, uniform sampling is used. Jan 27, 2013 at 16:19
• well I am not aware exactly what you asked but I guess it is uniform sampling only Jan 27, 2013 at 16:27
• Duty cycle typically means the pulse width of the sampling clock. Impulses will not alter the frequency response of sampled data, but practical sampling signals are not impulses. As the pulse width of the sampling signal increases, the frequency content of the sampled signal becomes more rolled off (the reconstructed version that is). A classica case of this effect is called the sample and hold effect. You can investigate this a a modulation problem, with the sampling pulse as the carrier signal. Jan 27, 2013 at 16:27

## 2 Answers

First establish the following convention:

$$DutyCycle = \frac{SampleClockOnTime}{SampleClockPeriod}$$

In the following discussion,

$$SampleClockOnTime = T_p$$ $$SampleClockPeriod = T_s$$

You can model the effects of $T_p$ on your recovered signal as a pulse amplitude modulation signal recovery problem. The sample clock signal is a pulse with finite duty cycle. The reconstruction signal starts by modulating the sample clock signal with the data values of your sampled signal. Literally you can think of multiplying your samples values by a unit amplitude pulse (your sample clock) to create a physical time sequence.

In the frequency domain, you end up with a reconstructed signal that has altered frequency characteristics (roll off at the high frequencies) that are a direct consequence of the sample clock pulse width (aka duty cycle).

To complete the recovery of your signal, you will pass the modulated pulse signal through a low pass filter to obtain only the baseband components of the signal. The resulting signal with have frequency magnitude characteristis of the form:

$$|F'(f)| = |F(f)||\frac{T_psin(pifT_p)}{T_s*f*T_p}$$

Where: F'(f) is the recovered signal and F(f) is the spectrum of the origianl sampled signal

The effects of the sample clock pulse width is represented by: $$\frac{T_psin(pifT_p)}{T_s*f*T_p}$$

If you plot this, you will see the amplitude rolls off as frequency approaches the sample clock frequency and the roll off is becomes more pronounced as $T_p$ increases.

You can look for more information on this by searching on the topic of "Sample and Hold effect". Most of the work I've seen on this topic is in the context of switched capacitor filters (which is how I was exposed to it).

If the sampler is edge triggered, and the changing duty cycle affects the edge doing the triggering (leading or trailing), then there will be sampling jitter. If the sampler is pulse gated (for example, some capacitor in a sample-and-hold circuit being (dis)charged by the input signal for most of the duration of the pulse), then a change in duty cycle that affects the center of the gating pulse can cause sampling jitter. Sampling jitter can produce a similar effect to that of frequency modulation of the signal, with the modulator being the timing noise or variation.