I work on a simulation decimation filter: downsampling + filter.
My test environment: low data rate receiver, BPSK, square root raised cosine filter with cutoff frequency =0.5, transition bandwidth = 0.2, sampling frequency = 4 and 21 taps.
I am not an expert in signal processing but I have to know some stuff.
My question is about downsamplig step. Downsampling for me as software engineer means that I need discard N sample between two samples.
I implemented in this way decimation and got additional frequencies. Matlab simulation doesn’t give these frequencies.
If I sum up, it will work as in Matlab.
where o - sample i use, x samples I discard
I sum sample "o" and 3 samples "x" up if a downsampling factor is 4. Resultant is a new sample =^ "0"
This works in FPGA, but I cant understand it why it works...could someone gives me an explanation or if this operation exists how can I seach information about it?
Thank you in advance!