I did a FIR filter hardware implementation with 80 taps (FPGA/VHDL). I will use it later as the decimation filter.
- Does the number of taps affect a cost of implementation of FIR?
FIR filters belong to the class of linear filters, the combination of N lower order filters can create the desired FIR filter of the higher order. So I was thinking If it makes sense to implement the combination of N lower order filters instead of a one 80 taps filter?
- Is the decimation implemented in one stage usually?
- What is a difference between "filter ( convolution)", " polyphase filter" and "polyphase filter bank"?
Honestly, I dont know ny difference in an implementation.