Another question related to fixed point saturation and rounding. Say using notation S<WL, FW> where S means it is signed number, WL is the full bitwidth, and FW is the fractional bitwidth. So S<16, 15> means a 16-bit signed number that has 15-bit fractional bits.
Normally in a N-tap filter, denote input as S<x_WL,x_FW> and coefficients are S<c_WL,c_FW>. Then each multiplication would be S<x_WL+c_WL, x_FW+c_FW> and the N-tap output y would grow S<x_WL+c_WL, x_FW+c_FW> by log2(N) bits to S<x_WL+c_WL+log2(N), x_FW+c_FW>. Finally y's bitwidth S<x_WL+c_WL+log2(N), x_FW+c_FW> would be saturated and round off to S<y_WL, y_FW> where y_FW = x_FW+c_FW-round_off, and the part to the left of decimal point of y would be y_WL-y_FW.
Beside this routine approach, what other ways to limit internal bit growth, for example, in individual multiplication output S<x_WL+c_WL, x_FW+c_FW> and final output? There were some papers on designing the coefficients so that each multiplication can guarantee only grow 1-bit. But what else can be done?