I like the Rice's book as it gives enough details and explanations to be able to get to working implementation with a full understanding of what is actually happening. So the following is basically a citation from Rice.
1. What are the differences in PLL implementation?
A phase locked loop (PLL) in general has three basic components: a phase detector, a loop filter and a voltage controlled oscillator (VCO) arranged in a feedback system (see Appendix C in Rice's book). Digital PLL will have a somewhat similar structure. The goal of the PLL is to force the phase error to be zero.
Any PLL holds this basic structure. But for the tasks of synchronization (carrier and timing recovery) the particular implementation of PLL will depend on the algorithm you choose for a phase detector. Also it differs in where the feedback connection of the PLL goes.
2. What should be first: carrier or timing recovery?
In the section "10.1 Advanced Discreet-Time Architectures" Rice gives the review of different receiver architectures. For example, this is a "third generation discrete-time detector":
It shows the placement of PLLs for carrier recovery and symbol timing. Here you can see, that corrections from Symbol Timing PLL occur before the ones from Carrier Phase PLL. Note, that Rice also describes other architectures, which differ in where the feedback connections go.